In-situ low wafer temperature oxidized gas plasma surface treatm

Details In-situ low wafer temperature oxidized gas plasma surface treatm In-situ low wafer temperature oxidized gas plasma surface treatm

1997-03-24

1999-01-12

Bowers, Charles

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

438761, 438695, 438631, 438789, 438782, 438626, 438697, 438780, H01L 21283

Patent

active

058588825

ABSTRACT:
A method of forming an interlevel dielectric layer without peeling or cracking in the fabrication of an integrated circuit device is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is provided overlying the semiconductor device structures and a first conducting layer is provided overlying the insulating layer and extending down through the insulating layer to contact one of the semiconductor device structures. A first dielectric layer is deposited overlying the first conducting layer. A spin-on-glass layer is coated over the first dielectric layer and then etched back wherein a polymer builds up on the spin-on-glass surface. The spin-on-glass layer is treated with an oxygen plasma treatment wherein the treatment neutralizes the polymer buildup and prevents cracking and peeling of the spin-on-glass layer. A TEOS layer is deposited overlying the spin-on-glass layer to complete the interlevel dielectric layer. A via opening is etched through the interlevel dielectric layer to the first conducting layer. A second conducting layer is deposited within the via opening and patterned to complete the fabrication of the integrated circuit device.

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patent: 5003062 (1991-03-01), Yen
patent: 5270267 (1993-12-01), Ouellet
patent: 5334554 (1994-08-01), Lin et al.
patent: 5556806 (1996-09-01), Pan et al.
patent: 5635425 (1997-06-01), Chen
patent: 5679211 (1997-10-01), Huang

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