In-situ integrated oxide etch process particularly useful...

Details In-situ integrated oxide etch process particularly useful... In-situ integrated oxide etch process particularly useful...

1998-11-30

2002-04-30

Gulakowski, Randy (Department: 1746)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S724000, C438S743000, C438S744000, C438S906000, C438S954000, C216S039000, C216S072000, C216S080000

Reexamination Certificate

active

06380096

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to plasma etch processes used in the manufacture of semiconductor integrated circuits. In particular, the invention relates to an in situ integrated process for etching layered dielectric structures serving as inter-level dielectric layers.
BACKGROUND ART
The technology of fabricating semiconductor integrated circuits continues to advance in the number of transistors, capacitors, or other electronic devices which can be fabricated on a single integrated circuit chip. This increasing level of integration is being accomplished in large part by decreasing the minimum feature sizes. Even as the number of layers in the integrated circuit continues to increase, advanced processes are being developed which allow for a reduction in the number of processing steps for a functional layer. However, these advanced processes often make extraordinary demands upon the chemistry of the etching process. Dielectric etching has presented some of the most difficult demands.
In the past the common materials for inter-level dielectric have been based upon silicon, such as silicon dioxide, silica glass such as BPSG, and related silicon-based oxide materials that serve as electrical insulators. Recently, interest has developed in insulating materials with low dielectric constants (low-k dielectrics), some of which are based upon silicon but others are based upon carbon.
Advanced integrated circuits contain multiple wiring layers separated from the silicon substrate and from each other by respective dielectric layers. Particularly logic circuitry, such as microprocessors, require several layers of metallization with intervening inter-level dielectric layers. Small contact or via holes need to be etched through each of the dielectric layers. The contact or via holes are then filled with a conductor, composed typically of aluminum in the past but more recently composed of copper. A horizontal wiring layer is formed over one dielectric layer and then covered by another dielectric layer. The horizontal wiring and the underlying vias are often referred to as a single wiring layer. The conventional process not only fills the contact or via holes but also overfills them to form a thick planar layer over both the filled holes and the dielectric. Conventionally, a metal lithographic step then photographically defines a photoresist layer over the planar metal layer and etches the exposed metal into a network of conductive interconnects.
In contrast, a recently developed damascene process substitutes chemical mechanical polishing for metal etching. A dual-damascene structure, as illustrated in sectioned orthographic view in
FIG. 1
, has been proposed for advanced chips which avoids the metal etching and combines the metallization of the via and horizontal interconnect. There are two general types of dual-damascene processes, self-aligned and counterbore, both of which produce the structure of FIG.
1
.
A substrate
10
includes a conductive feature
11
in its surface. If the substrate
10
already includes a wiring level at its surface, the conductive feature
11
is metallic and may be a previously formed dual-damascene metallization. The interconnection between two metallic wiring levels is called a via. Conventionally, the metal forming the metallization has been aluminum and its alloys, but advanced integrated circuits are being designed with copper metallization. Alternatively, the conductive feature
11
may be a doped region in a silicon substrate
10
, for example, a source or drain. In this case, the interconnection between the silicon layer and a first metallization layer is called a contact. Although some aspects of the present invention apply to contacts, the major portion of the disclosure and the details of the invention are directed to vias, particularly copper vias and underlying copper lines
11
.
Over the substrate
10
and the included conductive feature
11
are deposited a lower stop layer
12
, a lower dielectric layer
14
, an upper stop layer
16
, and an upper dielectric layer
20
. The stop layers
12
,
16
have compositions relative to those of the dielectric layers
14
,
20
such that an etch chemistry is available which effectively etches a vertical hole in the overlying dielectric layer
14
,
20
but stops on the stop layer
12
,
16
. That is, the etch selectively etches the dielectric layer over the stop layer. Alternatively stated, the dielectric etch is selective to the stop material. As mentioned before, more advanced circuits are being designed with the two dielectric layers
14
,
16
being composed of a dielectric material having a lower dielectric constant than that of silicon dioxide. However, the specific examples of the invention use silicon dioxide, related non-stoichiometric materials SiO
x
, and related silica glasses for the dielectric. Some related glasses are borophosphosilicate glass (BPSG) and fluorinated silica glass (FSG), which exhibit much the same chemistry as SiO
2
. These materials will be hereafter collectively be referred to as oxides. The typical stop material for oxide is silicon nitride (Si
3
N
4
) although non-stoichiometric ratios SiN
x
, are included where x may be between 1.0 and 1.5. These materials will hereafter be referred to as nitrides. An advantage of the combination of oxide and nitride is that the both materials can be grown in a single reactor by plasma-enhanced chemical vapor deposition (PECVD). For example, silicon dioxide is grown under PECVD using tetraorthosilicate (TEOS) as the main precursor gas. Silicon nitride can be grown in the same reactor using silane as the main precursor in the presence of a nitrogen plasma. These examples are non-limiting and simply show the advantage of the vertical structure.
The dual-damascene etch structure shown in
FIG. 1
is formed in the previously described vertical structure. The discussion with respect to the invention will disclose at least one way of performing the dual-damascene etch. The result is that a generally circular via hole
18
is etched through the lower oxide layer
14
and the lower nitride stop layer
12
to reach the underlying conductive feature
11
. Multiple such via holes
18
are etched to reach different ones of the conductive features
11
. A trench
22
extending along the surface of the substrate
10
is etched through at least the upper oxide layer
20
and usually through the upper nitride stop layer
16
.
After completion of the dual-damascene etch structure of
FIG. 1
, the trench
22
and vias
18
are filled with a metal such as aluminum or copper. Physical vapor deposition (PVD) is the usual process for depositing the metal though it may be combined with chemical vapor deposition (CVD) or replaced by electro or electroless plating. Barrier layers are usually first conformally coated in the hole being filled. A typical barrier for copper includes Ta/TaN. The metal is deposited to a thickness that overfills the trench
22
and also covers a top planar surface
30
of the upper oxide layer
30
. Chemical mechanical polishing (CMP) is applied to the top surface of the wafer. CMP removes the relatively soft exposed metal but stops on the relatively hard oxide layer
20
. The result is a horizontal metal interconnect within the trench
22
and multiple vertical metal interconnects (vias) in the via holes
18
.
In the past, equipment limitations have required the frequent transfer of a semiconductor integrated circuit wafer being process from one vacuum processing chamber to another. Exposure of the wafers to the air environment during the transfer between vacuum chambers often results in corrosion of the metal features of the partially processed integrated circuit. The well known susceptibility of copper to corrosion in air increases the destructive risk. Also, carbon-based residue that forms on the interior of the reactor chamber over time can redeposit on exposed copper surfaces. Since these carbon based residues can be extremely difficult to remove from copper, their presence can adversely impact upon subsequent fo

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