In situ hard mask approach for self-aligned contact etch

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S700000, C438S714000, C438S717000, C438S723000, C438S743000, C216S041000, C216S047000, C216S049000, C216S067000, C216S080000

Reexamination Certificate

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07078334

ABSTRACT:
According to one embodiment, a method (100) may include forming a first insulating layer over a semiconductor substrate (step102), forming a hard mask layer (step104), and forming a photoresist etch mask having a thickness of less than about 4,000 angstroms (step106). Such a reduced thickness may conventionally lead to uncontrolled etching and/or may require multiple steps to ensure feature formation. A method (100) may further include etching an opening through at least one half the thickness of the hard mask layer to form a hard mask (step108) and etching through a first insulating layer without first removing a photoresist layer (step110). Such etching can essentially consume a photoresist layer, however controllability can be maintained as etching may continue with a hard mask in place.

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