In situ dielectric stacks

Details In situ dielectric stacks In situ dielectric stacks

2001-11-14

2003-04-08

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

Reexamination Certificate

active

06544900

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods and equipment for forming dielectric stacks in integrated circuits, and particularly to in situ processing in the formation of dielectric stacks.
2. Description of the Related Art
High-temperature ovens, called reactors, are used to create structures of very fine dimensions, such as integrated circuits on semiconductor substrates. One or more substrates, such as silicon wafers, are placed on a wafer support inside the reaction chamber. Both the wafer and support are heated to a desired temperature. In a typical wafer treatment step, reactant gases are passed over the heated wafer, causing the chemical vapor deposition (CVD) of a thin layer on the wafer. Various process conditions, particularly temperature uniformity and reactant gas distribution, must be carefully controlled to ensure a high quality of the resulting layers.
Through a series of deposition, doping, photolithography and etch steps, the starting substrate and subsequent layers are converted into integrated circuits, with a single substrate producing from tens to thousands or even millions of integrated devices, depending on the size of the wafer and the complexity of the circuits.
Batch processors have traditionally been employed in the semiconductor industry to allow simultaneous processing of multiple wafers, thus economically presenting low processing times and costs per wafer. Recent advances in miniaturization and attendant circuit density, however, have lowered tolerances for imperfections in semiconductor processing. Accordingly, single wafer processing reactors have been developed for improved control of deposition conditions.
Among other process parameters, single wafer processing has greatly improved temperature and gas flow distribution across the wafer. In exchange for greater process control, however, processing time has become even more critical than with batch systems. Every second added to processing times must be multiplied by the number of wafers being processed serially, one at a time, through the same single-wafer processing chamber. While moving to larger wafers (e.g., from 200 mm to 300 mm wafers) improves throughput by packing more chips onto a single wafer, tolerance for yield loss is commensurately reduced due to the increased expense of each wafer. Conversely, any improvements in wafer throughput and/or yield can translate to significant fabrication cost savings.
One area in which process control is particularly critical is the fabrication of transistor gate dielectrics. In the pursuit of ever faster and more efficient circuits, semiconductor designs are continually scaled down with each product generation. Transistor switching time plays a large role in the pursuit of faster circuit operation. Switching time, in turn, can be reduced by reducing the channel length of the transistors. In order to realize maximum improvements in transistor performance, vertical dimensions should be scaled along with horizontal dimensions. Accordingly, effective gate dielectric thickness, junction depth, etc. will all decrease with future generation integrated circuits.
Conventional gate dielectrics are formed of high quality silicon dioxide and are typically referred to as “gate oxide” layers. Ultra thin gate oxides (e.g.,less than 5 nm), however, have been found to exhibit high defect densities, including pinholes, charge trapping states, and susceptibility to hot carrier injection effects. Such high defect densities lead to leakage currents through the gate dielectric and rapid device breakdown unacceptable for circuit designs with less than 0.25 &mgr;m gate spacing, i.e., sub-quarter-micron technology.
While care under laboratory conditions can be used to control defect densities, such control has been difficult to achieve under commercial volume fabrication conditions. Moreover, even if the integrity of the oxide is perfectly maintained, quantum-mechanical effects set fundamental limits on the scaling of gate oxide. At high fields, direct tunneling dominates over Fowler-Nordheim tunneling, and largely determines oxide scaling limits. These scaling limits have been estimated at about 2 nm for logic circuits, and about 3 nm for more leakage-sensitive memory arrays in dynamic random access memory (DRAM) circuits. See, e.g., Hu et al., “Thin Gate Oxides Promise High Reliability,” SEMICONDUCTOR INTERNATIONAL (July 1998), pp. 215-222.
Theoretically, incorporating materials of higher dielectric constant into the gate dielectric opens the door to further device scaling. Due to higher dielectric constant, a silicon nitride layer, for example, can exhibit the same capacitance as a thinner silicon dioxide layer, such that a lower equivalent oxide thickness can be achieved without tunnel-limited behavior. Another advantage of silicon nitride is its diffusion barrier properties, resisting boron penetration.
On the other hand, silicon nitride has been found to exhibit a higher density of defects, such as interface trapping states, as compared to oxides. One solution to the individual shortcomings of oxides and nitrides is to produce a hybrid layer. Incorporation of nitrogen into oxide, to form silicon oxynitride dielectric layers, has been found to improve the quality of gate dielectrics. See, e.g,. Leonarduzzi & Kwong, “Improving Performance with Oxynitride Gate Dielectrics,” SEMICONDUCTOR INTERNATIONAL (July 1998), pp. 225-230. This solution, however, results in a compromise in dielectric characteristics, exhibiting a lower effective dielectric constant as compared to a full silicon nitride gate dielectric.
Forming silicon nitride over thin oxide layers, however, has been found to reduce defect densities while considerably lowering overall gate dielectric equivalent oxide thickness. See, e.g., Kim et al., “Ultra Thin (<3 nm) High Quality Nitride/Oxide Stack Gate Dielectrics Fabricated by In-Situ Rapid Thermal Processing,” IEDM 97 (1997), pp. 463-466.
While nitride/oxide bilayers and oxynitride gate dielectric structures have proven promising in theoretical studies, incorporation into commercially viable process flows has been more difficult to achieve. Conventional processing technology has yet to satisfactorily achieve the high quality, defect-free layers required of ultrathin gate dielectrics with acceptable yield. Moreover, the increased complexity of multiple processing steps for formation of gate dielectric stacks significantly reduces wafer throughput and thereby increases fabrication costs.
Similar integration and cost problems have plagued another area in which high quality, thin dielectric layers are desirable. Integrated capacitors in memory arrays must exhibit a certain minimum capacitance for proper data storage and retrieval. As the chip area or “footprint” available per memory cell shrinks with each progressive generation of integrated circuits, the required capacitance per unit of footprint has increased. Many complex folding structures have been proposed for increasing capacitance through increased capacitor electrode surface area for a given cell footprint. Often, these structures require extremely complex fabrication steps, increasing the cost of processing significantly.
Other efforts to increase capacitance for a given memory cell space have focused on the use of materials characterized by high dielectric constants (high k materials). Certain metal oxides, such as barium strontium titanate (BST), strontium bismuth tantalate (SBT), tantalum oxide (Ta
2
O
5
), etc., exhibit high permittivity (k) and are thus promising for increasing capacitance. Integration of such materials into current process flows, however, has been challenging due to the relative instability of high k materials, a tendency to exhibit high defect densities, and the reduced benefit of high k materials in combination with native oxide over conventional electrodes.
A need exists, therefore, for effective methods of forming high quality dielectric layers. Desirably, such methods should be compatible with single-wafer proces

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