Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2002-01-29
2004-08-10
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S800000
Reexamination Certificate
active
06774055
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2001-43048 filed on Jul. 18, 2001.
BACKGROUND
1. Technical Field
The present invention relates to an overlay test of a semiconductor device, and more particularly, to a method for measuring an overlay accuracy of a semiconductor device in an in-line system.
2. Description of Related Art
High-integration of semiconductor devices is required to achieve high quality and low cost devices for competitiveness in the market. A method for fabricating high-integrated semiconductor devices comprises a scale-down process for making thinner gate oxide layers and shorter channels in transistors. According to recent trends, various fabricating technologies and relevant fabricating systems have been developed.
For mass production of semiconductor devices, each wafer is processed to construct an electronic circuit having an identical pattern on each chip of a wafer. The wafer processing comprises forming various layers on surfaces of semiconductor wafers every lot and etching certain portions of the wafers using pattern masks, selectively and repeatedly.
A photolithography process for fabricating semiconductor devices generally comprises the steps of coating, alignment, photo-exposure, development, overlay measurement and critical dimension measurement. The steps of coating and development are commonly performed with a spinner unit (or a track unit), and the steps of alignment and photo-exposure are generally performed with a stepper unit. These two units generally form in-line connection (so-called “an in-line system”) for sequentially performing the above steps. In other words, an in-line system comprises the steps of coating, alignment, photo-exposure and development.
After performing the steps of coating, alignment, photo-exposure and development, a step of overlay measurement is performed using an overlay measurement device to determine whether predetermined patterns of semiconductor devices are accurately aligned. The step of overlay measurement generally measures an accuracy of an overlay pattern formed at a scribe lane between main chips of a wafer. The overlay accuracy of semiconductor devices is measured by determining whether previous device patterns formed by a previous photolithography process are properly aligned with current device patterns formed by a current photolithography process. The step of overlay measurement comprises radiating a preset light beam onto aligned wafers and detecting any reflected light beam from the wafers to compare a level difference between the previous and current device patterns.
When wafers having a diameter of 8 inches or smaller are fabricated, the step of overlay measurement is generally performed on only a few of wafers out of 25 wafers every lot in consideration of productivity of a processing line. However, when wafers are fabricated having a diameter of 12 inches or larger, the reliability of the overlay measurement decreases for each lot. For example, since a desired variance of an overlay accuracy is typically about 30 nm for highly integrated devices having a diameter of 17 inches or smaller, all wafers of a lot are checked for their overly accuracy, which may result in a variance of 20 nm. Thus, it is difficult to satisfy the desired variance for highly integrated semiconductor devices in measuring all wafers of a lot. Moreover, as a wafer diameter increases, the possibility of overlay faults increases. Furthermore, if a quarter micro design rule is applied to wafers having a diameter of 12 inches or larger, an alignment distribution fault of various wafers may cause a massive yield distribution fault. Because of such problems, a raw cost burden may be imposed in manufacturing wafers having a diameter of 12 inches.
Because the conventional overlay accuracy measurement method has disadvantages of decreasing reliability as the diameter of wafers increase and an alignment distribution fault, a whole yield test should be performed to check an overlay accuracy of all wafers in each lot.
FIG. 1
shows an in line system for performing a conventional overlay accuracy measurement method, in which a local overlay measurement device
30
is separately installed from in-line devices, i.e., a spinner
10
and a stepper
20
.
FIG. 2
shows conventional overlay measurement steps. In
FIG. 1
, steps S
10
, S
20
, S
30
and S
40
respectively indicate coating, alignment, photo-exposure and development of a photo-resistant layer. As shown
FIG. 2
, after performing an in-line process
100
(which comprises steps of coating
102
, alignment & photo-exposure
104
, development
106
and one lot process completion check
108
), an overlay accuracy measurement step
112
for sample wafers is performed after a lot end step
110
.
The conventional overlay measurement method has a disadvantage of a relatively long measurement time. For instance, if it takes about 10 minutes to measure an overlay accuracy of one wafer, it will be take multiple hours to measure the overlay accuracy of all wafers of each lot, and thus, mass production performance decreases. That is, because a user transports wafers to the overlay measurement device
30
to measure the overlay accuracy of sample wafers after completion of the development step (S
40
of FIG.
1
), an entire yield test requires longer time for measuring an overlay accuracy, thereby decreasing mass production performance.
As described above, a conventional overlay measurement method has disadvantage in that wafers should be loaded in a measurement device that is separate from in-line devices, thereby resulting in production delay, a reduction in the yield and a greater probability of wafer contamination. Further, a user's mistake or other job-related complexities in inputting a correction value into the stepper
20
to complement the measurement accuracy decreases the reliability in measurement of the overlay accuracy.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for performing an in-line overlay accuracy measurement, which is capable of solving disadvantages associated with conventional methods.
It is another object of the present invention to provide an in-line system and a method thereof, in which an in-line overlay accuracy measurement is performed after a development step, which is capable of simplifying wafer processing and reducing time for measuring overlay accuracy.
It is further object of the present invention to provide an in-line system having an overlay measurement function and a method thereof capable of performing an overlay accuracy measurement of a wafer having a larger diameter.
According to one aspect of the present invention, there is provided a system for performing wafer processing comprising a stepper for performing alignment and photo-exposure of a wafer and a spinner, in-line connected to the stepper, for performing coating and development of the wafer, and an overlay measurement device, in-line connected to the spinner, for automatically measuring an overlay accuracy of the wafer after wafer development is completed by the spinner.
According to another aspect of the present invention, there is provided a method for performing wafer processing in a system comprising a stepper, a spinner and an overlay measurement device. The method comprises the steps of: aligning and photo-exposing a wafer with the stepper; coating and developing the wafer with the spinner; and automatically measuring an overlay accuracy of the wafer with the overlay measurement device after the wafer developing step is completed, wherein the overlay measurement device is in-line connected to the spinner.
According to further aspect of the present invention, there is provided a method for performing wafer processing. The method comprises the steps of: performing an in-line process comprising the steps of alignment, photo-exposure, coating and development of a wafer; and automatically performing an overlay accuracy of the wafer without discharging the wafer after the wafer deve
Choi Jae-Young
Park Tae-Sin
F. Chau & Associates LLC
Pham Long
Samsung Electronics Co,. Ltd.
Trinh Hoa B.
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