4. Apparel
  5. General structure
  6. Pockets

Joseph Siegel

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Automated decoupling capacitor insertion

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Implementation of an assertion check in ATPG models

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and system for monitoring and profiling an integrated...

Data processing: measuring – calibrating – or testing – Measurement system – Temperature measuring system
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Pocket device

Apparel – General structure – Pockets
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Scannable latch for a dynamic circuit

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
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Profile ID: LFUS-PAI-P-1444016

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