Impact ionization MOSFET method

Details Impact ionization MOSFET method Impact ionization MOSFET method

2011-03-01

2011-03-01

Nguyen, Khiem D (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21409

Reexamination Certificate

active

07897469

ABSTRACT:
A method of manufacturing an I-MOS device includes forming a semiconductor layer (2) on a buried insulating layer (4). A gate structure (23) including a gate stack (14) is formed on the semiconductor layer, and used to (5) self align the formation of a source region (28) by implantation. Then, an etch step is used to selectively etch the gate structure (23) and this is followed by forming a drain region (36) by implantation. The method can precisely control the i-region length (38) between source region (28) and gate stack (14).

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Choi, Woo Young, et al; “80nm Self-Aligned Complementary I-MOS Using Double Sidewall Spacer and Elevated Drain Structure and Its Applicability to Amplifiers With High Linearity”; EEMD 04-203; pp. 8.5.1-8.5.4, Dec. 2004.
Gopalakrishnan, Kailash, et al; “Impact Ionization MOS (I-MOS)—Part II: Experimental Results”; IEEE Transactions on Electron Devices; vol. 52. No. 1; Jan. 2006; p. 77-84.
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Choi, Woo Young, et al; “A New Fabrication Method for Self-Aligned Nanoscale I-MOS (Impact-Ionization MOS)”; pp. 211-212; Device Research Conference 2004; IEEE Cat No. 04TH8724; IEEE; Piscataway, NJ, US.

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