ILD stack with improved CMP results

Details ILD stack with improved CMP results ILD stack with improved CMP results

2005-03-22

2005-03-22

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S692000

Reexamination Certificate

active

06869836

ABSTRACT:
An ILD dielectric layer stack and method for forming the same, the method includes a semiconductor substrate including CMOS transistors with gate electrode portions; depositing a first layer including phosphorous doped SiO2over the semiconductor substrate to a thickness sufficient to cover the gate electrode portions including intervening gaps; depositing a second layer of undoped SiO2over and contacting the first layer to a thickness sufficient to leave a second layer thickness portion overlying the first layer following a subsequent oxide chemical mechanical polish (CMP) planarization process; carrying out the oxide CMP process to planarize the second layer and leave the second layer thickness portion; and forming metal filled local interconnects extending through a thickness portion of the first and second layers.

REFERENCES:
patent: 5895239 (1999-04-01), Jeng et al.
patent: 5950102 (1999-09-01), Lee
patent: 6274424 (2001-08-01), White et al.

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