Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-11-13
2001-02-06
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C382S145000, C438S010000, C714S733000
Reexamination Certificate
active
06185707
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit (IC) chip test software systems.
2. State of the Art
Digital semiconductor chips may be divided into two main categories, memory chips and logic chips. A microprocessor is one example of a logic chip. Digital semiconductor chips are designed by skilled chip designers using sophisticated software tools. Because of the difficulty of testing such chips, a field known as Design For Test (DFT) has emerged. One DFT technique involves designing into the chip one or more “scan chains” that may be used to write and read portions of the chip that would otherwise be inaccessible. Layout tools are used to lay out a chip design onto silicon. The resulting chip layout may be represented in the form of a netlist, i.e., a list of low-level design cells and the interconnections between them. The chip layout may also be represented in the form of a physical design file representing multiple layers of polygons. Once the design is completed, the part is “taped out” (i.e., files representing the chip are written to tape or disk). One format used for such files is the GDSII format. A mask house then makes photomasks used to manufacture the chip.
Both memory chips and logic chips require production monitoring and testing. Production monitoring is performed using “in-line” inspection equipment, and production testing is performed using “end-of-line” test equipment. In-line inspection equipment inspects entire semiconductor wafers, each of which may have formed thereon hundreds of chips. End-of-line test equipment performs “binsort functional test” on semiconductor wafers in which the pads of chips are contacted and the chips “exercised.” At the conclusion of functional test, parts are “binned” (typically, placed in different categories within an electronic record) according to the test results.
Apart from production testing is failure analysis. Failure analysis attempts to identify the cause of failures of chips of a particular chip design after those failures have been detected during production (or prototype) testing. Failure analysis may typically require more detailed failure information than just a bin code. Detailed failure information is typically obtained by retesting a limited number of packaged parts.
Memory chips, because of their structure as regular arrays of memory cells, readily lend themselves to failure analysis. A memory chip may be tested by performing a series of read and write operations to the memory chip. Errors in read/write testing may be pin-pointed as likely physical defects at readily-identifiable locations on the chip. Alternatively, the memory chip design may contain built-in self-test (BIST) capabilities. In either case, functional test results can be “bitmapped” to failure locations on the memory chip. In memory bitmapping, electrical failures are localized within a relatively small physical “trace” on the die.
Process flow in accordance with conventional memory bitmap testing is illustrated in
FIG. 1. A
wafer is subjected to both in-line inspection (right-hand column) and end-of-line testing (left-hand column). In-line inspection may be performed, for example, using optical inspection equipment such as the KLA21xx series available from KLA Tencor. In-line inspections produce defect files containing X,Y location optical defect information. This information may then be output in any convenient format, an example of which is a format used by the Yield Manager tool of, Knights Technology. End-of-line testing is performed using a tester, sometimes referred to as ATE (Automatic Test Equipment). The tester identifies failed memory locations. This information is processed to identify X,Y defect locations. The X,Y defect information may also be output to the Yield Manager tool. Because in-line and end-of-line defect information is in the same format within the Yield Manager tool, a combined defect overlay may be obtained, enabling “killer defects” (defects that render a part non-functional) to be identified. In particular, if the locations of a defect and a failure coincide, the defect may be presumed to a be a killer defect, i.e., a direct cause of the failure, in which case trouble-shooting would then focus on the production process rather than the underlying design of the part.
As a result of the greater testability of memory chips, yield enhancement organizations within semiconductor manufacturing plants, or fabs, have long relied on memory chips to de-bug a given generation of technology. Yield enhancement engineers have typically used a memory production line to monitor the production process and ensure yield on other production lines of logic products using the same technology. For yield enhancement of memory chips, in-line defect inspection tools have been used, together with end-of-line functional test bitmap results. Memory bitmap failure data may be further summarized into failure categories (e.g., single-bit failure, column failure, row failure, etc.).
Given coordinates of memory failures, failure analysis engineers can use a variety of “physical deprocessing” methods to identify the root cause of the failure. Based on the failure category, engineers can estimate where in the production process the failure occurred (e.g., the polysilicon layer deposition step, the metal
1
layer deposition step, etc.).
However, in recent years, the market share of logic products within the semiconductor industry has greatly increased, resulting in many new “logic-only” fabs being brought on-line. Unfortunately, without the benefit of a “memory line monitor,” logic-only fabs cannot take full advantage of yield enhancement techniques developed within the industry over many years. The logic-only yield enhancement engineer today is severely handicapped when compared to counterparts in fabs that run memory products. Heretofore, there has been no way to “bitmap” area of logic within a chip. Furthermore, logic chip functional test results do not provide a starting point for the physical coordinates of failures within a failed die.
The most advanced logic chip designs contain scan testing. Scan testing breaks the logic real estate of a chip into many discrete chains of logic which can be tested individually for basic functionality. Scan testing enables a list of failing signals to be identified. However, even after a list of failing signals is produced for a given die, it is still not possible to find the physical location of the failure because each failing signal may contain hundreds of transistors within its “cone of logic,” and there are usually multiple failing signals. Traditional logic chip yield enhancement techniques therefore rely heavily on correlation of binsort functional test results to anticipate and correct semiconductor process issues. This approach suffers from several drawbacks, including: the inability to relate a particular bin's fallout to a suspect process level; the inability to distinguish pre-packaging yield issue from packaging yield issues; and the inability to establish a clear link between large populations of failed die.
Failure analysis may make use of a known electrical diagnosis process whereby a diagnostic list of suspected failing nets may be obtained as shown in FIG.
2
. Packaged devices having BIST (scan) capabilities are tested using a tester. Scan failure data is translated into format that can be used by an ATPG (Automatic Test Pattern Generation) tool, e.g., an ATPG tool used previously to generate test pattern files used by the tester. The ATPG tools uses the translated test data, together with the test pattern files, setup files, one or more ATPG diagnostic models, and design information from a design database in order to identify suspected failing nodes, output in the form of a diagnostic list (FIG.
3
).
CAD navigation tools have been developed to aid in failure analysis. CAD navigation refers to the ability to point and click within a circuit layout display and by so doing automatically drive a piece of equipment such as FIB (Foc
Balachandran Hari
Parker Jason
Smith Shawn
Burns Doane Swecker & Mathis L.L.P.
Cady Albert De
Knights Technology, Inc.
Lamarre Guy
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