IC chip package with directly connected leads

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S692000

Reexamination Certificate

active

06249041

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and in particular to an integrated circuit (IC) chip package with directly connected leads.
BACKGROUND OF THE INVENTION
In the field of power semiconductors, and in particular in the field of power MOSFETs, the performance of a product is determined by the ability of the product to act as an ideal switch for a high current. Performance therefore depends on the ability of the product to provide a near-infinite resistance in the off state and a near-zero resistance in the on state.
Recent advances in power MOSFET technology have significantly reduced the on-state resistance of the semiconductor components of power MOSFET devices, making the contact metallization resistance and package resistance a significant part of the device on-state resistance. Thus, to achieve further significant reductions in on-state resistance, the metallization and package resistance must be reduced.
In addition, the resistance in a power MOSFET device generates heat which must be removed to maintain high performance. Cooling of power MOSFET devices is fundamentally limited by current device configurations. Even in vertical power MOSFET devices, a majority of the heat generated in a power MOSFET device is generated in the top 10 microns of the semiconductor die. Because thermally conductive packaging such as ceramic packaging is expensive, a thermally insulative packaging material such as plastic is typically used. Thus, to reach a cooling surface, the heat generated near the top surface of the die must either travel through the bond wires and leads, which can conduct only a limited amount of heat, or through the semiconductor to the back side of the die. Since the thermal conductivity of silicon cannot be significantly changed, significant advances in heat removal require a device configuration that allows better thermal transport from the top side of the die.
SUMMARY OF THE INVENTION
Therefore, a need has arisen for a semiconductor device that addresses the disadvantages and deficiencies of the prior art. In particular, a need has arisen for a semiconductor device with reduced electrical and thermal resistance contributions from the package.
Accordingly, an improved semiconductor device is disclosed. In one embodiment, the semiconductor device includes a semiconductor chip with a plurality of contact areas on either the top or bottom surface. A first lead assembly, formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to one of the contact areas of the semiconductor chip. The first lead assembly has at least one lead connected to and extending from the lead assembly contact. A second lead assembly, also formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to another one of the contact areas of the semiconductor chip. The second lead assembly has at least one lead connected to and extending from the lead assembly contact. An encapsulant encloses the semiconductor chip, the lead assembly contact of the first lead assembly and the lead assembly contact of the second lead assembly.
A technical advantage of the present invention is that the semiconductor device has low electrical and thermal resistance contributions from the package. Another technical advantage of the present invention is that lead frames with chip contact areas smaller than the chip itself are used, thereby allowing a smaller package size and more efficient utilization of the limited surface area available on a printed circuit board. Yet another technical advantage is that the semiconductor device may be formed as either a leaded package or a leadless chip carrier package.


REFERENCES:
patent: 4935803 (1990-06-01), Kalfus et al.
patent: 5365106 (1994-11-01), Watanabe
patent: 5544412 (1996-08-01), Romero et al.
patent: 5665996 (1997-09-01), Williams et al.
patent: 5821611 (1998-10-01), Kuboto et al.
patent: 6040626 (2000-03-01), Cheah et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

IC chip package with directly connected leads does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with IC chip package with directly connected leads, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and IC chip package with directly connected leads will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2538868

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.