IC chip package structure and underfill process

Details IC chip package structure and underfill process IC chip package structure and underfill process

2006-12-12

2006-12-12

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With dam or vent for encapsulant

C257S778000, C257S783000, C257S753000, C257SE23127, C257SE23160, C257SE21514

Reexamination Certificate

active

07148560

ABSTRACT:
A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. The process includes providing a dam structure on a carrier substrate; attaching solder bumps of an inverted flip chip to the carrier substrate; injecting an adhesive material between the flip chip and the carrier substrate at multiple injection points located along adjacent edges of the flip chip; and injecting a sealant material around the adhesive material. During application of the adhesive material and the sealant material to the IC package structure in the underfill process, the dam structure reduces stress applied to the corners of the flip chip. This prevents or at least reduces de-lamination of dielectric layers on the flip chip.

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patent: 6376923 (2002-04-01), Sumita et al.
patent: 6459144 (2002-10-01), Pu et al.
patent: 6465743 (2002-10-01), Owens
patent: 6933173 (2005-08-01), Yunus
patent: 63-62362 (1988-03-01), None

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