I/O ESD protection device for high performance circuits

Details I/O ESD protection device for high performance circuits I/O ESD protection device for high performance circuits

2011-06-07

2011-06-07

Smith, Zandra (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

07955923

ABSTRACT:
A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors. In these embodiments, either an N+/PLDD diode or an implanted diode is formed in place of one of the transistors.

REFERENCES:
patent: 5594265 (1997-01-01), Shimizu et al.
patent: 6621108 (2003-09-01), Tashiro et al.
patent: 6873506 (2005-03-01), Chen et al.

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