HSQ processing for reduced dielectric constant

Details HSQ processing for reduced dielectric constant HSQ processing for reduced dielectric constant

1997-10-23

1999-03-30

Bowers, Charles

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438788, 438622, 438624, 438637, 438761, 438763, 438692, H01L 21316

Patent

active

058889116

ABSTRACT:
Patterned metal layers are gap filled with HSQ and heat soaked in an oxidizing environment prior to oxide deposition by PECVD and planarization. Heat soaking is confined to less than about 10 seconds to minimize the dielectric constant of the HSQ layer.

REFERENCES:
patent: 5506177 (1996-04-01), Kishimoto et al.
patent: 5548159 (1996-08-01), Jeng
patent: 5656555 (1997-08-01), Cho
patent: 5728630 (1998-03-01), Nishimura et al.
Konecni et al., "A Stable Plasma Treated CVD Titanium Nitride Film for Barrier/Glue Layer Applications," Jun. 18-20, 1996, VMIC Conference, 1996 ISMIC -106/96/0181(c), pp. 181-183.
Kim et al., "Stability of TiN Films Prepared by Chemical Vapor Deposition Using Tetrakis-dimethylamino Titanium," J. Electrochem. Soc., vol. 143, No. 9, Sep. 1996, The Electrochemical Society, Inc., pp. L188-L190.
Iacoponi et al., "Resistivity Enhancement of CVD TiN with In-Situ Nitrogen Plasma and Its Application In Low Resistance Multilevel Interconnects," Advanced Metalization and Interconnection System for ULSI Applications, 1995 (5 pages).
Eizenberg et al., "Chemical vapor deposition TiCN: A new barrier metallization for submicron via and contact applications," J. Vac. Sc. Technol. A 13(3), May/Jun., 1995, 1995 American Vacuum Society, pp. 590-595.
Eizenberg et al., "TiCN: A new chemical vapor deposited contact barrier metallization for submicron devices," (3 pages).
Hillman et al., "Comparison of Titanium Nitride Barrier Layers Produced by Inorganic and Organic CVD," Jun. 9-10, 1992, VMIC Conference, 1992 ISMIC-101/92/0246, pp. 246-252.
Liu et al., "Integrated HDP Technology for Sub-0.25 Micron Gap Fill," Jun. 10-12, 1997, VMIC Conference, 1997 ISMIC -107/97/0618(c), pp. 618-619.
Bothra et al., "Integration of 0.25.mu.m Three and Five Level Interconnect System for High Performance ASIC," Jun. 10-12, 1997, VMIC Conference, 1997 ISMIC -107/97/0043(c), pp. 43-48.
Wang et al., "Process Window Characterization of ULTIMA HDP-CVD.RTM. USG Film," Feb. 10-11, 1997, DUMIC Conference, 1997 ISMIC -222D/97/0405, pp. 405-408, 619.
Saikawa et al., "High Density Plasma CVD for 0.3.mu.m Device Application," Jun. 18-20, 1996, VMIC Conference, 1996 ISMIC -106/96/0069(c), pp. 69-75.
Nguyen et al., "Characterization of High Density Plasma Deposited Silicon Oxide Dielectric for 0.25 Micron ULSI," Jun. 27-29, 1995, VMIC Conference, 1995 ISMIC -104/95/0069, pp. 69-74.

Affiliated with

Also associated with

Rating

HSQ processing for reduced dielectric constant does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with HSQ processing for reduced dielectric constant, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and HSQ processing for reduced dielectric constant will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1214635