High voltage transistor of semiconductor memory devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438451, H01L 218238, H01L 2176

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active

058307907

ABSTRACT:
The present invention relates to a high voltage transistor of a semiconductor memory device, and more particularly to a high voltage transistor which improves element isolation and breakdown voltage characteristics thereof. A high voltage transistor formed on a semiconductor substrate comprising a first and second diffusion regions doped by a first conductive impurity which are separated from each other by a channel region doped by a second conductive impurity, the channel region, and a gate electrode interposing a gate oxide layer, the first and second diffusion regions and the channel region being surrounded with an oxide layer for isolating elements having a second conductive channel stop layer on the lower portion thereof, characterized in that the density of a second conductive impurity doped in the regions where a boundary area in a direction of channel length of each of the first and second diffusion regions is contacted with a boundary area of the oxide layer for isolating elements is lower than that of a second conductive impurity doped in the regions where a boundary area in a direction of channel width of each of the first and second diffusion regions is contacted with the boundary area of the oxide layer for isolating elements.

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"An ASIC-Compatible EEPROM Technology", 1992 IEEE Custom Integrated Circuits Conference. Month Unknown.

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