High speed sensing device in a semiconductor memory device

Details High speed sensing device in a semiconductor memory device High speed sensing device in a semiconductor memory device

1991-10-15

1993-11-02

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

365149, 36518909, 365206, 3072961, G11C 700

Patent

active

052589560

ABSTRACT:
The present invention for increasing the sensing speed of the input/output line by preventing the potential difference between the bit line pair from being decreased when the bit line is connected to input/output line in a DRAM. A semiconductor memory device has a column gate connected between a bit line pair and an input/output line pair. A sense amplifier with a discharging node is connected to the bit line pair, and a pull down transistor has an electrode for controlling a current flow path which is disposed between the discharging node and a ground voltage node. A PMOS transistor has a channel between the charging node and an output node connected to the control electrode of the pull down transistor, and has a gate connected to a given first signal. A NMOS transistor has a channel between the output node and the ground voltage node, and has a gate connected to the first signal. A first booster receiving the first signal, has a first capacitor operating according to the first signal, being connected to the output node, and a second booster receiving a given second signal, has a second capacitor operating according to the second signal, being connected to the output node. A control signal generating circuit receives the second signal in order to generate a control signal to the column gate.

REFERENCES:
patent: 71093 (1887-04-01), Kitano
patent: 4503522 (1985-03-01), Etoh et al.
patent: 4704706 (1987-11-01), Nakano et al.
patent: 4811903 (1989-03-01), Watanabe
patent: 4980863 (1990-12-01), Ogihara

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