4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

London Jin

Inventor

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Boundary-scan cells with improved timing characteristics

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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High speed boundary scan design

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Low power scan test cell and method for making the same

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Patent

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Profile ID: LFUS-PAI-P-1849287

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