Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-05
2001-06-12
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S640000, C438S638000, C438S633000, C438S634000, C438S786000
Reexamination Certificate
active
06245669
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
The present invention relates to semiconductor devices in general, and more particularly to semiconductor devices having anti-reflective coatings and hard masks to aid in photolithography steps, such as those used to form in a dual damascene interconnect structure and gate electrodes.
2) Description of the Prior Art
The semiconductor industry's continuing drive toward integrated circuits with ever decreasing geometries, coupled with its pervasive use of highly reflective materials, such as polysilicon, aluminum, and metal suicides, has lead to increased photolithographic patterning problems. Unwanted reflections from these underlying reflective materials during the photoresist patterning process often cause the resulting photoresist patterns to be distorted.
Anti-reflective coatings (ARCs) have been developed to minimize the adverse impact due to reflectance from these reflective materials. In many instances, these ARCs are conductive materials which are deposited as a blanket layer on top of metal and simultaneously patterned with the metal to form interconnects. A problem with these ARCs is that many of these materials cannot be used in applications such as dual damascene, wherein the metal layer is not patterned. In a dual damascene application, openings are formed in the interlayer dielectric, and the metal is blanket deposited in those openings and subsequently polished back to form a planar inlaid plug. In such application, the metal layer is never etched and therefore, any conductive ARC on top of the inlaid metal would cause the metal plugs to be electrically short circuited together through the conductive ARC.
Some dielectric ARCs are also known, such as conventional silicon rich silicon nitride or aluminum nitride, but a disadvantage with these conventional ARCs is that they are most suitable for deep ultraviolet (DUV) radiation, whereas a vast majority of photolithography steps occur at higher wave lengths such as I-line or G-line where these ARCs are not optimal.
Accordingly, there is a need for an improved semiconductor manufacturing operation which utilizes an anti-reflective coating that is applicable to the more prevalent I-line or G-line lithographies and which can be used in applications, such as dual damascene, which require ARCs that are nonconductive and potentially used as a damascene etch stop layer.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,378,659 (Roman) shows a Si-Rich SiN layer as an ARC layer for DUV.
U.S. Pat. No. 5,252,515 (Tsai et al.) shows a Si-Rich Silicon oxynitride barrier layer.
U.S. Pat. No. 4,871,689 (Bergami) shows a Si-rich Silicon oxynitride layer for a dielectric filled trench.
U.S. Pat. No. 4,870,470 (Bass et al.) shows a Si rich Silicon oxynitride layer for a charge trapping layer in an EEPROM.
U.S. Pat. No. 5,741,626 (Jain) shows a dual damascene process.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a Dual damascene interconnect structure using a Novel Si-rich SiON ARC etch barrier layer.
It is an object of the present invention to provide a method for fabricating a Dual damascene interconnect structure using a Novel Si-rich SiON ARC etch barrier layer and special silicon oxide etch that has a high selectivity to Si-Rich SiON and SiN.
It is an object of the present invention to provide a method for fabricating gate using a Novel Si-rich SiON ARC etch barrier layer (hard mask) that has a Si-rich SiON self aligned contact (SAC) structure.
It is an object of the present invention to provide process to form a Si Rich SiON layer and an SiO
2
etch process implemented in two preferred embodiments: {circle around (1)} a Dual damascene structure and {circle around (2)} a self aligned contact (SAC) structure.
It is an object of the present invention to provide an SiO
2
etch process that has a higher etch selectivity of Si-Rich SiON to oxide than compared with that of SiON and PE nitride.
It is an object of the present invention to provide a method for fabricating a capacitor having a high density and capacitance.
In general the invention teaches a specialized process for forming structure using a Si rich Silicon oxynitride (SiON) etch stop layer (refractive index (RI)=2.7 measured at 633 nm). This Si-rich SiON layer can also be used as an ARC film for I-line photo.
The invention has two preferred embodiments where the invention's Si rich SiON layers are used in semiconductor structures: {circle around (1)} a dual damascene structure with using the invention's Si rich SiON etch stop layer and {circle around (2)} a polysilicon line/gate self aligned contact (SAC) structure where the invention's Si rich SiON etch stop layer.
A second major feature of the invention is a specialized SiO
2
etch that has a high selectivity for invention's Si-rich SiON.
Generally, the first embodiment of the present invention involves using a dielectric phase of Si Rich Silicon oxynitride Anti-Reflection Coating (ARC) layer in conjunction with damascene or dual inlaid metalization processing. Specifically, a conductive region/line is provided overlying the surface of a semiconductor wafer. A damascene-type contact is etched to expose the conductive region. The invention's damascene process involves deposition of two dielectric layers with a Novel Si Rich silicon oxynitride ARC layer in the middle as an etch stop material. An opening with a small width (via) is formed using the Novel Si Rich silicon oxynitride Anti-Reflection Coating (ARC) layer as an etch stop. In a key step, a specialized SiO
2
etch process is used to form a larger opening (interconnect trench). The specialized SiO
2
etch is specifically designed to be used with the invention's Si rich SiON layer. The photolithographic processing used to form this damascene contact is alos benefited by the use of the antireflective coating (ARC) Si rich SiON layer. In order to reduce reflected light, reduce destructive and constructive interference from reflective light, and reduce adverse effects of light reflection during photoresist processing, an antireflective coating (ARC) layer is formed overlying the patterned inlaid conductive region to function as an anti-reflective coating (ARC).
The use of this dielectric phase antireflective coating (ARC) layer provides several advantages. First, the invention's etch and Si-Rich SiON antireflective coating (ARC) layer allow use of a very thin layer. This decreases the RC delay. The antireflective coating (ARC) layer has superior light absorption qualities beyond other known ARC layers when I line photo processing is used. In addition, the dielectric phase of antireflective coating (ARC) layer is non-conductive and will therefore not produce electrical short circuits of the inlaid damascene structure. In addition, the antireflective coating (ARC) layer may be deposited between the two dielectric layers (or oxide layers) to replace the convention SiN layer so that the antireflective coating (ARC) layer can serve the dual purpose of being an anti-reflective coating and being an etch stop layer used to form the damascene contact. In addition, the antireflective coating (ARC) layer may be deposited directly on top of the underlying conductive region as a barrier layer which prevents atoms of copper or like atoms from diffusing into adjacent dielectric regions.
A second major feature of the invention is the highly selective Si-Rich SiON to SiO
2
or SiN etch process. There are two process options are described below.
The Second embodiment of the invention is the Si-Rich SiON self aligned contact (SAC) structure. The Si-Rich SiON self aligned contact (SAC) structure has SiON spacers and capping layers that provide anti-r
Fu Chu Yun
Jang Syun-Ming
Tsai Chia Shiung
Ackerman Stephen B.
Bowers Charles
Nguyen Thanh
Saile George O.
Stoffel William J.
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