High selectivity oxide etch process for integrated circuit...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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Details

C438S714000, C438S723000, C156S345420

Reexamination Certificate

active

06171974

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for plasma etching oxide in an integrated circuit structure using a mixture of silicon tetrafluoride (SiF
4
) and one or more other fluorine-containing etchant gases in the presence of a silicon surface. More particularly, this invention relates to a high selectivity plasma etch process for preferentially etching oxide, with respect to silicon, in an integrated circuit structure, using a mixture of SiF
4
and one or more other fluorine-containing etchant gases and a silicon surface, which plasma etch process may be used with either capacitive discharge or electromagnetically coupled type plasma generators.
2. Description of the Related Art
Oxide layers typically are utilized as insulation, overlying silicon or silicon-containing surfaces, e.g., single crystal silicon such as a silicon wafer, epitaxial silicon, polysilicon, or silicides such as titanium silicide in integrated circuit structures. Such oxide layers may be selectively etched, for example, to form vias for formation of conductive contacts to the underlying silicon. Conventionally such oxide etches are carried out in a plasma etch process utilizing one or more fluorine-containing etch gases such as, for example, CF
4
, CHF
3
, CH
2
F
2
, CH
3
F, C
2
F
6
, NF
3
, SF
6
, etc.
When conventional capacitive discharge plasma generators are utilized in such prior art oxide etching processes, the pressure in the etch chamber is typically maintained at about 100 to 1000 milliTorr (1 Torr), resulting in a selectivity, with respect to silicon, of about 20:1. That is, oxide is preferentially etched instead of silicon by a ratio of about 20:1.
However, the use of such a high pressure during the etch adversely affects control of the etch profile. For example, to achieve vertical walls in 0.35 micrometer (&mgr;m) diameter contacts and/or vias, lower pressures of below 200 milliTorr, preferably below 30 milliTorr, and typically about 10 milliTorr, must be used. However, at such low pressures, the use of a conventional parallel plate capacitive discharge type plasma generator may result in a low etch rate and higher peak to peak voltage, necessitating the use of another type of plasma generator such as an electromagnetically coupled type plasma generator.
While the use of a pressure of about 10 milliTorr and a plasma generated by an electromagnetically coupled plasma generator does result in the etching of contact holes with vertical walls, the selectivity to silicon of such an etch system, using the previously discussed fluorine-containing etch gas chemistry, is reduced to about 6:1, probably due to the difficultly of polymer formation in such a low pressure environment and the more aggressive nature of the higher density plasma which results from the use of such an electromagnetically coupled plasma generator instead of the capacitive discharge type plasma generator.
Such a low selectivity may be satisfactory for a highly planarized structure and for perfectly uniform etch/plasma chamber conditions. However, such a low selectivity is unacceptable in many applications where it is highly desirable to etch as little silicon as possible once such silicon is exposed during the etching of the overlying oxide. For example, it is desirable, in some instances, to etch less than about 50 Angstroms (5×10
−3
&mgr;m) of underlying silicon during the oxide etch.
Such conventional plasma oxide etch processes, using one or more conventional fluorine-containing etch gases, usually rely on the formation of a polymer to inhibit etching of the silicon, wherein liberation of oxygen, during etching of the oxide, breaks down the polymer on the oxide surface, while the absence of such generated oxygen prevents breakdown of the polymer over silicon surfaces. It is, therefore, necessary to increase such polymer generation to achieve a higher selectively than the above mentioned 6:1 oxide to silicon etch ratio for electromagnetically coupled type plasmas.
However, such an increase in polymer formation increases the selectivity of the process at the expense of a reduction of the oxide etch rate, a reduction of the process window, and an increase in the chances for particle formation. This, in turn, can result in an unacceptable reduction in throughput of the process and a reduction of device yield.
It would, therefore, be desirable to provide an oxide etch process which would exhibit high selectivity to silicon, even when used at low pressure, e.g., about 10 milliTorr, with an electromagnetically coupled plasma generator, without any substantial reduction in etch rate of the oxide material.
SUMMARY OF THE INVENTION
The oxide etch process of the invention comprises the plasma etching of oxide over a silicon-containing surface using a mixture of SiF
4
gas and one or more fluorine-containing etchant gases to provide a process having high selectivity with respect to the silicon-containing surface. Preferably the etch chamber in which the process is carried out also contains an exposed silicon surface.
In a preferred embodiment, the etch process of the invention is carried out at a pressure of from about 1 to about 30 milliTorr, typically about 10 milliTorr, using a plasma generated by an electromagnetically coupled plasma generator. The etch process may, however, be used at higher pressures of from about 50 to about 200 milliTorr, typically about 100 milliTorr, using a plasma which may be generated by either the above-mentioned electromagnetically coupled plasma generator or by a capacitive discharge (parallel plate) type plasma generator.
The oxide etch process of the invention exhibits high selectivity to silicon of as much as 30:1, i.e., oxide is etched at a rate as much as 30 times the etch rate of silicon, regardless of the type of plasma generator utilized, or the pressure utilized within the broad range of from about 1 to about 200 milliTorr.


REFERENCES:
patent: 4350578 (1982-09-01), Friesh et al.
patent: 4368092 (1983-01-01), Steinberg et al.
patent: 4401054 (1983-08-01), Matsuo et al.
patent: 4427516 (1984-01-01), Levinstein et al.
patent: 4492620 (1985-01-01), Matsuo et al.
patent: 4675073 (1987-06-01), Douglas
patent: 4711698 (1987-12-01), Douglas
patent: 4778561 (1988-10-01), Ghanbari
patent: 4786359 (1988-11-01), Stark et al.
patent: 4793897 (1988-12-01), Dunfield et al.
patent: 4807016 (1989-02-01), Douglas
patent: 4810935 (1989-03-01), Boswell
patent: 4855017 (1989-08-01), Douglas
patent: 4918031 (1990-04-01), Flamm et al.
patent: 4948458 (1990-08-01), Ogle
patent: 5006220 (1991-04-01), Hijikata et al.
patent: 5074456 (1991-12-01), Degner et al.
patent: 5078833 (1992-01-01), Kadomura
patent: 5176790 (1993-01-01), Arleo et al.
patent: 5266154 (1993-11-01), Tatsumi
patent: 5423945 (1995-06-01), Marks et al.
patent: 5477975 (1995-12-01), Rice et al.
patent: 5556501 (1996-09-01), Collins et al.
patent: 0 644 584 A1 (1995-03-01), None
patent: 55-154581 (1979-05-01), None
patent: 55-044613 (1980-03-01), None
patent: 55-154581 (1980-12-01), None
patent: 59-003018 (1984-01-01), None
patent: 61-184823 (1985-09-01), None
patent: 62-142326 (1985-12-01), None
patent: 61-053732 (1986-03-01), None
patent: 61-224423 (1986-10-01), None
patent: 61-264729 (1986-11-01), None
patent: 62-7268 (1987-02-01), None
patent: 62-089882 (1987-04-01), None
patent: 62-142326 (1987-06-01), None
patent: 64-057600 (1987-08-01), None
patent: 63-9120 (1988-01-01), None
patent: 64-15928 (1989-01-01), None
patent: 2-62038 (1990-03-01), None
Bariya et al., A surface kinetic model for plasma polymerization with application to plasma etching,J. Electrochem.Soc., vol. 137, No. 8, Aug. 1990, pp. 2575-2581.
Butterbaugh et al., “Plasma-surface interactions in fluorocarbon etching of silicon dioxide,”J.Vac.Sci.Technol. B, vol. 9, No. 3, May/Jun. 1991, pp. 1461-1470.
J.W. Coburn, “Increasing the etch rate ratio of SiO2/Si in fluorocarbon plasma etching,”IBM Technical Disclosure Bulletin, vol. 19, No. 10, Mar. 1977.
Maurer et al., “Selective etching of oxide in a CF4/H2plasma,” Abstract No

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