High reliability memory element with improved delay time

Details High reliability memory element with improved delay time High reliability memory element with improved delay time

2006-05-30

2006-05-30

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S201000, C714S797000, C714S799000, C327S199000

Reexamination Certificate

active

07054203

ABSTRACT:
In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a voting structure/settable memory element set an identical logical value into each settable memory element, and the voting structure/settable memory element. After the settable memory elements, and the voting structure/settable memory element are set, the voting structure/settable memory element with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the voting structure/settable memory element. The propagation delay through the voting structure/settable memory element is the only propagation delay of the triple redundant latch.

REFERENCES:
patent: 6882201 (2005-04-01), Koch et al.
patent: 6930527 (2005-08-01), Cabanas-Holmen et al.
patent: 6937527 (2005-08-01), Lotz et al.
patent: 2005/0251729 (2005-11-01), Lotz et al.

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