High performance redundancy in an integrated memory system

Details High performance redundancy in an integrated memory system High performance redundancy in an integrated memory system

1996-07-22

1998-01-13

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Bad bit

365194, G11C 700

Patent

active

057086133

ABSTRACT:
The preferred embodiment of the present invention provides a memory system for use in a computer system that improves the performance of a bit redundancy steering mechanism. The preferred embodiment provides a timing signal path to the bit steering mechanism with a delay shorter than that to the memory data array. Additionally, the required address signals are provided to the bit steering mechanism before the addresses are provided to the memory data array. This is preferably accomplished by bypassing the buffers and providing the address signals directly to the bit steering mechanism.

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