4. Static information storage and retrieval
  5. Read/write circuit
  6. Bad bit

Mark Beiley

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Dual word enable method and apparatus for memory arrays

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent

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High performance redundancy in an integrated memory system

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Test circuit for delay lock loops

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage
Reexamination Certificate

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Profile ID: LFUS-PAI-P-543717

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