Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-06-10
2004-11-23
Flynn, Nathan J. (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S218000, C438S246000, C438S248000, C438S289000, C257S510000, C257S068000, C257S296000, C257S394000
Reexamination Certificate
active
06821857
ABSTRACT:
BACKGROUND
The present invention relates generally to semiconductor device manufacturing and, more particularly, to an embedded dynamic random access (eDRAM) device having a high on-current for high performance thereof.
In the integrated circuit (IC) industry,.-manufacturers have been embedding dynamic random access memory (DRAM) arrays on the same substrate as microprocessor cores or other logic devices. This technology is commonly referred to as embedded DRAM (eDRAM). Embedded DRAM provides microcontrollers and other logic devices with faster access to larger capacities of on-chip memory at a lower cost than other currently available systems having conventional embedded static random access memory (SRAM) and/or electrically erasable programmable read only memory (EEPROM).
At the same time, the semiconductor industry continually strives to increase semiconductor device performance and density by miniaturizing the individual semiconductor components and by miniaturizing the overall semiconductor device dimensions. For example, the semiconductor device density can be increased by more densely integrating the components on the semiconductor chip. However, increasing integration densities by placing the individual circuit elements in closer proximity increases the potential for interactions between the circuit elements. Therefore, it has become necessary to include isolation structures to prevent any significant interaction between circuit elements on the same chip.
Contemporary CMOS technologies generally employ field effect transistors that are adjacent or bounded by trenches. These trenches provide isolation (shallow trench isolation or “STI”) for the semiconductor devices. As is known in the art, the close proximity of each semiconductor device to an edge or corner of the trench may create parasitic leakage paths. These parasitic leakage paths result from an enhancement of the gate electric field near the trench corners, the gate electric field in turn being enhanced by the trench corner's small radius of curvature and the proximity of the gate conductor. As a result of the enhanced gate electric field, the trench corner has a lower threshold voltage (V
t
) than the planar portion of the device.
Ideally, in an eDRAM device, the DRAM is embedded within the logic without affecting the performance of the logic device. However, as a practical matter, there are device design constraints imposed by the logic processing steps, such as relating to spacer and oxide thicknesses. These processes are kept preferably the same for the DRAM, so that the manufacturing costs of the eDRAM may be minimized. At the same time, the eDRAM should include a high performance DRAM, meaning that the on-current of the DRAM devices should remain high, (even as device dimensions shrink), without compromising the device off-current. Unfortunately, this becomes more and more difficult as cell and device size shrinks. In particular, the reduced diffusion width of the DRAM devices in succeeding technologies has a proportionate impact (i.e., a decrease) on the device on-current. Accordingly, it is desirable to be able to fabricate a reduced width eDRAM device that is still a high-performance device by having a relatively high on-current capability.
SUMMARY
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for enhancing the on-current carrying capability of a MOSFET device. In an exemplary embodiment, the method includes recessing fill material formed within a shallow trench isolation (STI) adjacent the MOSFET so as to expose a desired depth of a sidewall of the STI, thereby increasing the effective size of a parasitic corner device of the MOSFET. The threshold voltage of the parasitic corner device is then adjusted so as to be substantially equivalent to the threshold voltage of the MOSFET device.
In another aspect, a semiconductor device includes a MOSFET disposed adjacent a shallow trench isolation (STI). The MOSFET includes a gate oxide layer formed over an active device area and a corner region defined by the STI, the STI further having a sufficient amount of fill material therein removed so as to allow the formation of the gate oxide layer to increase the effective size of a parasitic corner device. The corner region is further implanted with a dopant so as to adjust the threshold voltage of the parasitic corner device to be substantially equivalent to the threshold voltage of the MOSFET.
In yet another aspect, an embedded, dynamic random access memory (eDRAM) device includes an array of memory storage devices associated with a plurality of MOSFET devices for accessing the memory storage devices, wherein each of the MOSFET devices is disposed adjacent a shallow trench isolation (STI). Further, each of the MOSFET devices includes a gate oxide layer formed over an active device area and a corner region defined by the STI. The STI has a sufficient amount of fill material therein removed so as to allow the formation of the gate oxide layer to increase the effective size of a parasitic corner device. The corner region is further implanted with a dopant so as adjust the threshold voltage of the parasitic corner device to be substantially equivalent to the threshold voltage of the MOSFET.
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Cheng Tzyy-Ming
Divakaruni Rama
Iyer Subramanian S.
Khan Babar A.
Cantor & Colburn LLP
Flynn Nathan J.
Forde Remmon R.
Jaklitsch Lisa U.
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