High dielectric constant material deposition to achieve high...

Details High dielectric constant material deposition to achieve high... High dielectric constant material deposition to achieve high...

2000-01-05

2001-03-27

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S763000, C438S785000

Reexamination Certificate

active

06207584

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to high dielectric constant layers with improved dielectric characteristics provided by employing a nucleation method prior to formation of the high dielectric constant layer.
2. Description of the Related Art
The art of semiconductor fabrication is driven by the desire to continually shrink device sizes and improve component capabilities. These goals are often contradictory. While decreasing sizes of devices provides a more efficient layout, component features such as dielectric films or layers are pushed to their limit. Often, materials or processes used to form these dielectric films or layers become inadequate for future chip generations. Deposition processes and dielectric materials are usually reduced in size along with the shrinking device dimensions. This often requires the reduced size dielectric material to electrically isolate components with at least the same capacity as earlier generations.
In other cases, improved dielectric layers not only provide less thickness or layout area but may also improve performance. For example, capacitor dielectric layers for stacked capacitors for dynamic random access memories (DRAM) include a high dielectric constant layer between two electrodes. Improvements in the dielectric layer between the electrodes provide a more reliable device and increase capacitance.
Referring to
FIG. 1
, major elements of a semiconductor memory cell are illustratively shown. Stacked capacitors
10
are shown having a top electrode
16
, a bottom electrode
18
and a capacitor dielectric layer
20
therebetween. Bottom electrode
18
is provided on a dielectric layer
19
and is connected to a plug
22
which extends down to a portion of active area
12
. Active areas
12
form an access transistor for charging and discharging stack capacitor
10
in accordance with data on a bitline
24
. Bitline
24
is coupled to a portion of active area
12
(source or drain of the access transistor) by a contact
23
. When a gate conductor
28
is activated the access transistor conducts and charges or discharges stack capacitor
10
. When the minimum feature size is reduced with each new generation of the memory design, stacked capacitor
12
loses area thereby reducing the capacitor's capabilities. Capacitor dielectric layer
20
may formed from a high dielectric constant material to increase capacitance. Barium strontium titanium oxide (BSTO) is typically employed.
BSTO may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD) or other processes. CVD is preferred to get high step coverage around the bottom electrode. In a one step CVD process, BSTO films are deposited at a constant temperature for a given time by controlling, primarily, the deposition pressure and BSTO composition. In a two step (or multi-step) deposition process, a first step is to deposit a continuous BSTO film at a lower temperature to obtain an amorphous film. A second step is employed to deposit another continuous BSTO film at a higher temperature to obtain a crystallized BSTO film. An anneal step is needed to crystallize the first layer of the amorphous BSTO film either before or after depositing the second BSTO film. Although BSTO provides a high dielectric constant layer between capacitor electrodes, it would be advantageous to increase the capabilities of the dielectric layer between the two capacitor electrodes to improve performance and reduce possible leakage.
Therefore, a need exists for a method for improving the dielectric characteristics of a deposited dielectric layer. A further need exists for a dielectric layer which has improved dielectric characteristic without cost to layout area and without increase to the thickness of the dielectric layer.
SUMMARY OF THE INVENTION
A method for forming a dielectric layer, in accordance with the present invention, includes exposing a surface to a first dielectric material in gaseous form at a first temperature. Nuclei of the first dielectric material are formed on the surface. A layer of a second dielectric material is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.
A method for forming a capacitor dielectric layer, in accordance wit the invention, includes forming a first capacitor electrode and exposing a surface of the first capacitor electrode to a first dielectric material in gaseous form at a first temperature. Nuclei are formed of the first dielectric material on the surface of the first capacitor electrode. A layer of a second dielectric material is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.
In other methods, the first dielectric material may includes one of a metal oxide and a metal titanate, and the second dielectric material may also include one of a metal oxide and a metal titanate. The first temperature may be less than about 500 degrees Celsius, and the second temperature may be greater than about 550 degrees Celsius. The step of forming nuclei of the first dielectric material may include exposing the surface to the first dielectric material for between about 2 to about 30 seconds. The step of forming a second capacitor electrode over the second dielectric layer to form a capacitor may be included. The capacitor may provide 50 fF to about 500 fF per square micron of electrode area. The first dielectric material and the second dielectric material may be the same. The first dielectric material and the second dielectric material may include barium strontium titanium oxide. The method may further include the step of preparing the first capacitor electrode by etching a surface of the first capacitor electrode.
A method for forming a stacked capacitor for a semiconductor memory device, in accordance with the present invention includes forming a first capacitor electrode, exposing a surface of the first capacitor electrode to barium strontium titanium oxide (BSTO) in gaseous form at a first temperature, and forming nuclei of the BSTO on the surface of the first capacitor electrode by adjusting at least one of gas composition, flow rate and pressure of the BSTO to provide a grain size and orientation of the nuclei. A dielectric layer is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.
In other methods, the first temperature may be between about 350 degrees and about 500 degrees Celsius, and the second temperature may be greater than about 550 degrees Celsius. The step of forming nuclei of the BSTO may include exposing the surface to the BSTO for less than about 100 seconds. The method may include the step of forming a second capacitor electrode over the dielectric layer to form a capacitor. The capacitor may provide 50 fF to about 500 fF per square micron of electrode area. The dielectric layer may include one of a metal oxide and a metal titanate. The step of annealing the dielectric layer may also be included.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 5102832 (1992-04-01), Tuttle
patent: 5494840 (1996-02-01), Ohmi
patent: 5569619 (1996-10-01), Roh
patent: 5728604 (1998-03-01), Rha et al.
patent: 5754390 (1998-05-01), Sandhu et al.
patent: 5783253 (1998-07-01), Roh
patent: 5843829 (1998-12-01), Kuramae et al.
patent: 5962069 (1999-10-01), Schindler et al.
patent: 5976931 (1999-11-01), Yew et al.
patent: 5976990 (1999-11-01), Mercaldi et al.
patent: 6033943 (2000-03-01), Gardner

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