High density plasma nitridation as diffusion barrier and...

Details High density plasma nitridation as diffusion barrier and... High density plasma nitridation as diffusion barrier and...

2000-02-24

2001-05-01

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S591000

Reexamination Certificate

active

06225169

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to gate dielectric layers formed during the construction of gated semiconductor devices, such as field effect transistors (FETs). More specifically, the present invention relates to a method of producing a silicon nitride barrier between a silicon surface and a gate dielectric layer.
2. Description of Related Art
In current semiconductor technologies, silicon oxide (SiO
2
) is often used for its insulating properties as a gate oxide. As device dimensions shrink into the deep submicron range in ultra scale integrated (ULSI) circuit applications, the gate dielectric thickness must decrease proportionally in FETs to approximately 3 to 3.5 nanometers. In this regime of ultra thin dielectrics, interfacial defects, defect precursors, and the diffusion of dopants through gate dielectrics play dominant roles in device performance and reliability.
There is a large body of experimental data for thin oxide dielectrics which demonstrates that: (i) hydrogen atom transport from polycrystalline silicon gate electrodes to the silicon-silicon oxide (Si—SiO
2
) interface under stressbias conditions generates interfacial traps and positively charged defects and (ii) nitrogen atom incorporation at Si—SiO
2
interfaces improves device reliability, while interfacial nitrogen-hydrogen bonding leads to high defect densities.
Polysilicon used as the gate electrode in a metal oxide semiconductor field effect transistor (MOSFET) device is normally doped with phosphorous to a concentration of greater than 10
21
cm
−3
to minimize the series resistance. Beneath the polysilicon gate is the gate oxide, and directly beneath the gate oxide is the channel that is typically more lightly doped by a factor of 10
4
. Since the gate oxide thickness in deep submicron devices is very thin, any small leakage of the gate electrode dopant into the channel shifts the device threshold and makes the device inoperative.
To prevent the leakage of the gate electrode dopant into the channel, it is known to deposit a nitride barrier layer between the gate oxide and the channel. Typically, a rapid thermal nitridation (RTN) process is used to deposit this nitride layer. The RTN process is relatively costly and slow because the wafers must be moved into different chambers during cleaning and depositing steps required for the RTN process. The RTN process also produces less uniform nitride layer than is desirable for ULSI devices.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a less expensive and faster nitridation process than the RTN process for the construction of gate dielectrics.
It is another object of the present invention to provide a more uniform nitride layer than is produced by the RTN process.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
This invention uses a high density plasma (HDP) method to produce silicon nitride layers. A major benefit of using HDP nitridation is that native oxide cleaning, carbon contamination of silicon surface cleaning, and silicon nitridation can all be performed as a single integrated process in a single chamber.
The silicon nitride layer is grown using an inductively coupled HDP source in multiple steps. The first step is to clean the native oxide formed on the silicon or polysilicon surface using an HDP plasma, preferably an HDP hydrogen plasma. This contamination cleaning can also be performed using an HDP oxygen plasma for fifteen seconds. To aid in cleaning, the silicon surface may also be bombarded with a pure HDP argon plasma.
The next step is to grow the silicon nitride layer on the clean silicon (or polysilicon) surface using the HDP nitridation method. This technique produces a very thin layer of a silicon nitride film (approximately 20 to 30 Å) on the silicon or polysilicon surface by exposing the wafer to pure nitrogen plasma. The plasma is preferably created using inductive coupling which is powered using a low radio frequency generator. The result is a uniform (<2%, 1&sgr;) nitride layer on the silicon or polysilicon surface.
After the above process is completed, the gate oxide is deposited. Another HDP nitridation process is then completed. in this step of the process, a thin layer of nitrided oxide is grown on the gate oxide film. This nitrided oxide film layer is also grown using the HDP process. This film serves to overcome the charge defeats described above as well as the diffusion barrier for the dopant.
More specifically, the present invention comprises a method of constructing a gate dielectric on a semiconductor surface which includes the steps of contamination cleaning the semiconductor surface in a chamber using a high density plasma of a first gaseous agent, growing a first silicon nitride layer on the semiconductor surface using a high density plasma of nitrogen, growing a gate dielectric layer on the silicon nitride layer, growing a second silicon nitride layer on the dielectric layer using a high density plasma of nitrogen, and depositing a conductive layer over the second silicon nitride layer to form a conductive gate.
In the preferred method of the invention the first gaseous agent in the step of contamination cleaning is hydrogen. In another embodiment of the invention the first gaseous agent in the step of contamination cleaning is oxygen. The step of contamination cleaning the semiconductor surface may alternatively comprise using a combination of a high density hydrogen plasma with a high density argon plasma.
In another aspect of the invention the high density plasma of nitrogen used in the step of growing a first silicon nitride layer on the semiconductor surface is formed by heating nitrogen gas with an inductively coupled radio frequency generator.
The step of growing a gate dielectric layer on the silicon nitride layer preferably includes growing a layer of silicon oxide on the silicon nitride layer to form the gate dielectric layer. In the most highly preferred method of the invention, the steps of contamination cleaning and growing a first silicon nitride layer are both completed in the same chamber without removing the semiconductor chip from the chamber.
The deposition temperature used during the step of growing a first silicon nitride layer on the semiconductor surface is most preferably between about 300 and 450° C. The invention is also directed to gated devices that have a gate dielectric constructed on a semiconductor surface by the method of the invention above.


REFERENCES:
patent: 6087238 (2000-07-01), Gardner et al.
patent: 6140187 (2000-10-01), Debusk et al.
Lee, D. R. et al. Reliability of Nitrided Si-Sio2Interface Formed by a New, Low-temperature, Remote-Plasma Process.Journal of Vacuum Science Technology,vol. 13, No. 4 (Jul./Aug. 1995), pp.1788-1793.
Ma, Yi et al. Si-Sio2Interfaces Formed by Remote Plasma-Enhanced Chemical Vapor Deposition of Sio2on Plasma-processed Si Substrates.Journal of Vacuum Science Technology,vol. 10, No. 4 (Jul./Aug. 19925), pp.781-787.

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