High current and/or high speed electrically erasable memory...

Details High current and/or high speed electrically erasable memory... High current and/or high speed electrically erasable memory...

2000-04-05

2003-02-25

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050, C257S314000, C257S315000

Reexamination Certificate

active

06525962

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to programmable logic devices, and more particularly to nonvolatile memory cells for use in programmable logic devices.
BACKGROUND OF THE INVENTION
Programmable logic has increasingly become a valued resource for system designers. Programmable logic can allow for a custom logic design to be implemented without the initial cost, delay and complexity of designing and fabricating an application specific integrated circuit (ASIC).
Currently, there are many variations of programmable logic, including simple programmable logic devices (SPLDs), complex PLDs (CPLDs), and field programmable gate arrays (FPGAs). Such devices typically include logic circuits and corresponding memory circuits. The particular function of a logic circuit can be determined according to data stored in a corresponding memory circuit. Some programmable logic arrangements can include switching circuits (also called programmable interconnects) that enable and/or disable switching paths according to data stored in a memory circuit.
A programmable logic memory circuit may be volatile or non-volatile. One particular example of a volatile memory circuit can be a static random access memory (SRAM) cell. A drawback to volatile approaches is that an ancillary non-volatile memory (such as a programmable read only memory (PROM)) is usually necessary. Upon power-up, data from a PROM can be loaded into SRAM cells of a programmable logic device. An advantage of volatile programmable logic can be the increased speed of such devices and/or a simpler manufacturing process technology. A disadvantage can be the volatile nature of such devices. A power-up/loading step, such as that described above, can introduce more delay into the startup operation of a device. Further, the addition of an ancillary non-volatile memory device may increase size and/or cost.
Non-volatile programmable logic typically does not require a power-up loading step. Currently, there are a number of approaches to forming non-volatile programmable logic. Such approaches may generally be categorized as “one time programmable” (OTP) or “in system programmable” (ISP). OTP devices may include approaches that use fuses, anti-fuses and/or electrically erasable read only memories (EPROMs). For the most part, once OTP devices are programmed, their functionality may not be changed. (EPROM based devices may include ultra-violet light windows for erasing, but typically at a prohibitively high increase in packaging cost).
In contrast to OTP devices, ISP devices may be reprogrammed. This can be a particularly valuable feature as designs may go through prototyping and/or revisions. Some ISP devices may be reprogrammed even after being soldered or otherwise connected to a circuit board. ISP devices may include programmable non-volatile memory devices such as electrically erasable and programmable read-only-memories (EEPROMs), including “flash” EEPROMs (which can allow for the rapid simultaneous erasure of multiple memory cells).
EEPROM structures (including flash EEPROM structures) typically utilize a floating gate that may be programmed and/or erased by placing charge on the floating gate. Various charge transport mechanisms can be utilized, including Fowler-Nordheim tunneling and/or channel hot electron injection, to name two examples.
Regardless of the particular programmable logic circuit structure employed, an increasing concern with programmable logic can be the operating speed and the power supply level requirement of such devices. An operating speed is typically the time required for applied input signals to generate corresponding output signals. Many aspects of a programmable logic design can impact operating speed. One aspect can include the speed at which memory cell data can be read. At the same time system speeds are increasing, the operating voltages of such systems are falling. Lower operating voltages may typically translate into lower operating speeds. For these and other reasons, it would be desirable to arrive at some way of increasing operating speed to compensate for speed reductions introduced by lower operating voltages.
Having described the general operation and variations of programmable logic devices, a particular conventional programmable logic memory cell will now be described. Referring now to
FIG. 3
, a conventional electrically erasable programmable logic device (EEPLD) cell is illustrated in a top plan view and designated by the general reference character
300
. An EEPLD cell
300
may be conceptualized as including a cell boundary
302
. A cell boundary
302
may define the limits of a repeatable structure within an integrated circuit. A mirror image repetition may be advantageous if contact sharing between adjacent cells is desirable.
A conventional EEPLD
300
may further include a first semiconductor region
304
and a second semiconductor region
306
. First and second semiconductor regions (
304
and
306
) may include diffusions regions formed in a semiconductor substrate. Such diffusion regions may be formed by ion implantation or other conventional methods. First and second semiconductor regions (
304
and
306
) may be bounded by isolation structures (not shown) such as those formed by LOCOS (local oxidation of silicon) or STI (shallow trench isolation), or gate structures, as will be described below.
A conventional EEPLD
300
may further include a select gate
308
and a floating gate
310
situated between a first and second semiconductor region (
304
and
306
). The conductivity between a first and second semiconductor region (
304
and
306
) may be controlled by the particular state of a select gate
308
and floating gate
310
. More particularly, a floating gate
310
may be programmed or erased, and thereby enable conductivity between the first and second semiconductor regions (
304
and
306
). In addition, a select gate
308
may be driven between a select and de-select potential and thereby enable conductivity between the first and second semiconductor regions.
Thus, when the select gate
308
is at a de-select potential, a relatively high impedance can exist between first and second semiconductor regions (
304
and
306
). However, when a select gate
308
is at a select potential, the impedance between first and second semiconductor regions (
304
and
306
) may depend upon a floating gate
310
. If a floating gate
310
is in one state (e.g., erased) a relatively high impedance can exist between first and second semiconductor regions (
304
and
306
). If a floating gate
310
is in another state (e.g., programmed) a relatively low impedance can exist between first and second semiconductor regions (
304
and
306
).
An alternate way of conceptualizing the conventional approach shown in
FIG. 3
is to consider a controllable current path Isense as existing between a first and a second semiconductor portion (
304
and
306
). The conductivity of the current path Isense may be controlled by a select gate
308
and a floating gate
310
.
FIG. 4
shows a side cross-sectional view taken along line
4
—
4
to illustrate such a current path Isense. It is understood that by reversing a voltage applied between a first and a second semiconductor portion (
304
and
306
), the direction of a current path Isense may be reversed.
In the example of
FIG. 3
, a first semiconductor region
304
may include a first sense contact
312
that may be connected to a sense amplifier (not shown). Similarly, a second semiconductor region
306
can include a second sense contact
314
that may also be connected to a sense amplifier. A select gate
308
may include a select contact
316
that can be connected to a select line (not shown). In this way, a select line can be activated to provide memory data to a sense amplifier. A sense amplifier can amplify this information and use such information to establish the functionality of one or more logic circuits in a PLD.
A conventional EEPLD cell
300
may also include a programming portion
318
and a charge storage portion
320
. A program

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