Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2000-06-07
2003-02-04
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S700000, C257S707000, C257S747000
Reexamination Certificate
active
06515347
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wafer level semiconductor device in which a plurality of chips and chip size packages (hereinafter referred to as CSP) are formed on a wafer, and a method of manufacturing the same.
2. Description of the Related Art
There has been proposed a semiconductor package in structure such that an external output terminal formed of a projected electrode is provided on a chip to shape a semiconductor device sealed by resin or the like as much as possible to a semiconductor element (hereinafter referred to as chip), at least a side surface of projected electrode is sealed by resin under the wafer condition and thereafter the wafer is cut to provide each chip. (Refer to the Japanese Published Unexamined Patent Application No. HEI 10-79362; U.S. patent application Ser. No. 09/029,608).
A wafer level semiconductor device is desirable to conduct various processes or test operations or the like under the wafer condition before the wafer is cut into separate chips.
FIGS.
12
(
a
),
12
(
b
) are diagrams illustrating an example of a method of manufacturing a wafer level semiconductor device of the related art.
FIGS.
12
(
a
) and
12
(
b
) are diagrams illustrating an example of a method of manufacturing a wafer level semiconductor device of the related art.
FIG.
12
(
b
) illustrates a process for forming the sealing resin
103
also by further providing the temporary film
104
on the lower mold die
106
, and shown in FIG.
12
(
a
).
However, when the wafer
101
is taken out from the upper and lower mold dies after the resin sealing process, the wafer is cooled to room temperature. Therefore, a problem arises in that a stress indicated by the arrow mark is applied to the wafer
101
, as illustrated in FIG.
12
(
c
), due to a difference in thermal expansion coefficients of the wafer
101
and sealing resin
103
, thereby warping the wafer
101
.
The wafer level semiconductor device in this warped condition will result in another problem, when the next process is to be carried out, that the wafer cannot be placed horizontally on the vacuum-holding tray or the like. Moreover, if the wafer is handled forcibly, the wafer
101
will probably be broken, as illustrated in FIG.
12
(
d
).
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a wafer level semiconductor device having a structure such that a sealing resin is formed on the wafer level semiconductor device and therefore the device is not warped even after it is taken out from the mold dies.
It is further object of the present invention to provide a method of processing the wafer level semiconductor device under the condition that the wafer is not warped.
The objects of the present invention are achieved by a wafer level semiconductor device comprising a wafer having a plurality of semiconductor elements formed on an upper surface thereof, a sealing resin including a first part for sealing the upper surface of the wafer and a second part for sealing a side surface of the wafer, the sealing resin having a lower edge surface flush with a lower surface of the wafer, and a film for covering the lower surface of the wafer and the lower edge surface of the second part of the sealing resin.
According to the wafer level semiconductor device described above, the entire part of the lower surface of the wafer and the lower edge surface of the second part of the sealing resin projected to the side surface of the wafer are covered with a film, and if a stress tending to warp the wafer is applied thereto, the film is placed in contact with the lower edge surface of the second part of the sealing resin and warpage of the wafer can therefore be prevented. A warping force is applied in the direction indicated by the arrow mark of FIG.
12
(
c
), but because the film is holding the second part of the sealing resin, warpage of the wafer can be prevented.
Further objects of the present invention are achieved by the method of manufacturing the wafer level semiconductor device comprising the step of preparing the wafer level semiconductor device also comprising the wafer on which upper surface a plurality of semiconductor elements are formed, the sealing resin including the first part for sealing the upper surface of the wafer and the second part for sealing a side surface of the wafer. The sealing resin having a lower edge surface flush with a lower edge surface of the wafer, and a film for covering the lower surface of the wafer and the second part of the sealing resin, and the processing step for manufacturing the wafer level semiconductor device under the condition that the film is provided.
According to the method of manufacturing the wafer level semiconductor device described above, because the wafer is handled under the condition that the film is bonded on the lower surface of the wafer, various processes may be executed under the condition that the wafer is not warped.
According to the wafer level semiconductor device achieved such that the second part of the sealing resin hangs over from the wafer, the wafer level semiconductor device can easily be taken out from the mold dies even when the sealing resin does not include the release agent.
According to the wafer level semiconductor device of the present invention, a groove is provided at the dicing position at the upper surface of the wafer, and the resin is thickly formed at the cutting position as a result of the resin filling the groove. Because the mechanical strength of this part increases, a stress applied to the wafer at the time of dicing can be alleviated. Moreover, release of sealing resin from the wafer due to the stress applied at the time of dicing can also be prevented.
According to the wafer level semiconductor device of the present invention, a part of the external circumference of wafer is cut and the area of the second part of the sealing resin which becomes the bonding area of sealing resin for bonding the film increases, sufficient bonding area can be reserved without a widening of the diameter of the sealing resin.
According to the wafer level semiconductor device of the present invention, the film is bonded and fixed only to the second part of the sealing resin. Thus, the film can be bonded without increasing the cost of material or the number of processes.
According to the wafer level semiconductor device of the present invention, the film has a line expanding coefficient which is greater than that of the sealing resin, and warpage of the wafer toward the sealing resin can be prevented.
According to the wafer level semiconductor device of the present invention, the film is provided with a slit in parallel with the radius direction of the wafer, and the film and rear surface of the wafer, which are closely held, can be separated easily because such slit previously serves as the peeling allowance for the film.
According to the method of manufacturing the wafer level semiconductor device of the present invention, the film is provided with a hole to expose the rear surface of the wafer and the wafer level semiconductor device is processed while the wafer is vacuum-held via the vacuum-holding hole, the wafer and the film can simultaneously be fixed to the mold dies through vacuum-sticking of wafer when it is set on the mold die.
According to the method of manufacturing the wafer level semiconductor device of the present invention, the hole in the film is shaped to conform to the groove provided on the vacuum-holding surface of mold die for vacuum-holding the film, and the amount of film sucked in the groove at the vacuum-holding surface can be reduced.
REFERENCES:
patent: 5008213 (1991-04-01), Kolesar, Jr.
patent: 5024970 (1991-06-01), Mori
patent: 5903044 (1999-05-01), Farnworth et al.
patent: 5903051 (1999-05-01), Miks
patent: 5907785 (1999-05-01), Palagonia
patent: 5969427 (1999-10-01), Wensel
patent: 6130111 (2000-10-01), Ikuina
patent: 6225205 (2001-05-01), Kinoshita
patent: 6326683 (2001-12-01), Houdeau et al.
patent: 6331449
Fukasawa Norio
Hozumi Takashi
Ikumo Masamitsu
Kawashara Toshimi
Shinma Yasuhiro
Armstrong Westerman & Hattori, LLP
Chaudhuri Olik
Fujitsu Limited
Ha Nathan W.
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