Semiconductor memory device and method of fabricating the same

Details Semiconductor memory device and method of fabricating the same Semiconductor memory device and method of fabricating the same

2001-06-25

2003-02-04

Booth, Richard (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S309000, C257S316000, C438S258000

Reexamination Certificate

active

06515326

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor memory device with a memory cell section including floating-gate type transistors and a capacitor section including capacitors, and a method of fabricating the device.
2. Description of the Related Art
Generally, it is important for semiconductor memory devices to increase the capacitance of capacitors and to decrease the chip area.
FIG. 1
shows schematically the layout of a prior-art semiconductor memory device, which has the memory cell section S
101
and the capacitor section S
102
on a semiconductor substrate.
The prior-art semiconductor memory device of
FIG. 1
is fabricated in the following way.
First, as shown in
FIG. 2A
, a silicon dioxide (SiO
2
) layer (not shown) with a thickness of 3 nm to 20 nm is formed on the surface of a p-type semiconductor substrate (e.g., a single-crystal silicon substrate)
110
. A silicon nitride (SiN
X
) layer (not shown) with a thickness of 100 nm to 200 nm is formed on the SiO
2
layer and is patterned to have a specific plan shape. Then, a SiO
2
layer is selectively formed on the exposed surface of the substrate
110
from the patterned SiN
X
layer, forming an isolation dielectric
114
. The isolation dielectric
114
thus formed defines active regions
110
a
on the substrate
110
.
Then, a first gate dielectric layer
112
with a thickness of 5 nm to 15 nm is selectively formed on the exposed surface of the substrate
110
in the active regions
110
a
by a thermal oxidation process.
An n-type polysilicon layer with a thickness of approximately 50 nm to 200 nm, which is doped with an appropriate dopant such as phosphorus (P), is formed over the entire substrate
110
to cover the isolation dielectric
114
and the active regions
110
a
. After a patterned resist film
118
is formed on the polysilicon layer, the polysilicon layer is selectively etched to form floating gates
120
on the gate dielectric layer
112
in the memory cell section S
101
and lower electrodes
122
on the isolation dielectric
114
in the capacitor section S
102
using the film
118
as a mask. The state at this stage is shown in FIG.
2
A.
After the patterned resist film
118
is removed, a dielectric layer
124
with a thickness of approximately 10 nm to 20 nm is formed over the substrate
110
by a thermal oxidation or chemical vapor deposition (CVD) process, covering the floating gates
120
in the memory cell section S
101
and the lower electrodes
122
in the capacitor section S
102
. The layer
124
has a three-layer structure; i.e., the layer
124
is formed by a SiO
2
sublayer, a SiN
X
sublayer, and a SiO
2
sublayer stacked in this order. Thus, the layer
124
is a so-called “ONO” layer. Next, an n-type polysilicon layer
126
with a thickness of approximately 100 nm to 200 nm is formed on the dielectric (ONO) layer
124
over the entire substrate
110
.
After a patterned resist film
128
is formed on the polysilicon layer
126
, the polysilicon layer
126
and the dielectric (ONO) layer
124
are selectively etched to define the memory cell section S
101
and the capacitor section S
102
on the substrate
110
using the film
128
as a mask. The state at this stage is shown in FIG.
2
B.
As seen from
FIG. 2B
, the remaining dielectric layer
124
in the memory cell section S
101
forms a second gate dielectric layer
124
a
and at the same time, the remaining polysilicon layer
126
in the memory cell section S
101
forms control gates
130
. The remaining dielectric layer
124
in the capacitor section S
102
forms a capacitor dielectric layer
124
b.
Subsequently, after the resist film
128
is removed, a patterned resist film
132
is formed on the polysilicon layer
126
thus patterned. Then, the polysilicon layer
126
is selectively etched to define the capacitors in the capacitor section S
102
using the film
132
as a mask. The state at this stage is shown in FIG.
2
C. As seen from
FIG. 2C
, the remaining polysilicon layer
126
in the capacitor section S
102
is divided to form upper electrodes
134
.
Thereafter, the patterned resist film
132
is removed, resulting in the structure shown in FIG.
2
D. Specifically, in the memory cell section S
101
, the first gate dielectric layer
112
, the floating gate
120
, the second gate dielectric layer
124
a
, and the control gate
130
in each of the active regions
110
a
constitute a floating-gate type transistor. In the capacitor section S
102
, the lower electrode
122
, the common capacitor dielectric
124
b
, and the upper electrode
134
constitute a capacitor.
As explained above, with the prior-art semiconductor memory device, each of the capacitors is located on the isolation dielectric
114
and is formed by the lower electrode
122
, the common capacitor dielectric
124
b
, and the upper electrode
134
. It is unlike the former, typical capacitor structure that is formed by a diffusion region in the substrate
110
, a gate dielectric layer, and a gate electrode. This is to suppress the parasitic capacitance existing in the capacitor section S
102
.
In recent years, the capacitor structure of the prior-art semiconductor memory device of
FIG. 1
tends to be insufficient to meet the need of further decreasing the chip area. To meet this need, an improvement has been created and disclosed, in which recesses are uniformly formed on the surfaces of the lower electrodes
122
in the capacitor section S
102
. This is to expand the surface area of each lower electrode
122
, thereby increasing the capacitance. Therefore, in this improvement, the chip area can be reduced without decreasing the capacitance of each capacitor.
However, in the improvement, there arises a problem about the withstand voltage. Specifically, since the lower electrode
122
has the recesses on its surface, the capacitor dielectric
124
b
extends along the recesses, resulting in a problem of degradation of the withstand voltage of the dielectric
124
b
. To ensure satisfactory withstand voltage, the dielectric
124
b
needs to be thicker, which means that the second gate dielectric layer
124
a
of each transistor in the memory cell area S
101
needs to be thicker as well. This is because the capacitor dielectric layer
124
b
and the second gate dielectric layer
124
a
are formed by the same dielectric layer
124
. As a result, there arises a problem that the performance or characteristic of the transistors in the memory cell section S
101
deteriorates.
As explained above, when the above-described improvement is adopted to increase the capacitance, the withstand voltage of the capacitor dielectric
124
b
in the capacitor section S
102
degrades. When the capacitor dielectric
124
b
is formed thicker to ensure its sufficient withstand voltage, the performance or characteristic of the transistors in the memory cell section S
101
deteriorates.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor memory device that makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric, and a method of fabricating the device.
Another object of the present invention is to provide a semiconductor memory device that makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the performance of characteristic of the memory cell section, and a method of fabricating the device.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, a semiconductor memory device is provided. This device comprises:
(a) a semiconductor substrate with an isolation dielectric;
the isolation dielectric defining active regions on the substrate;
(b) a memory cell section formed on the substrate;
the memory cell section including floating-gate type transistors for

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