Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-05
2001-11-27
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S211000
Reexamination Certificate
active
06323085
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an improved semiconductor structure for high density device arrays, and in particular to an improved split-gate transistor having high coupling, and to a process for its formation.
BACKGROUND OF THE INVENTION
Nonvolatile semiconductor memory devices based on metal-oxide-semiconductor field effect transistors (MOSFETs) are well-known in the art. There are currently three general types of MOSFET nonvolatile memory devices in use: EPROMs, EEPROMs, and flash EEPROMs. A flash EEPROM is comprised of an array of non-volatile storage cells from which data may be read any number of times without disturbing the state of the stored data. Each cell is an individual FET that stores a bit of information as the presence or absence of an electrical charge on a floating gate.
Typically EEPROMs are comprised of an array of paired transistors: a select or access transistor and a storage transistor. Many flash EEPROMs combine these two transistors into one device—a split-gate transistor with two gates sharing a single device channel. The control gate serves the function of the select or access transistor, and the floating gate serves as a storage device. The split-gate configuration alleviates the over-erase problem caused by Fowler-Nordheim tunneling, but results in a larger cell size.
Data is typically written to a cell by hot electron injection which occurs when a high positive voltage is applied to both the control gate and the drain line. Some of the electrons in the device channel will acquire sufficient energy to jump the energy barrier at the interface of the device channel and the tunneling oxide. Once they are in the tunneling oxide, the electrons are pulled toward the floating gate by the positive voltage on the control gate. This results in charge collection on the floating gate, which in turn affects the threshold voltage of the control gate.
Alternatively, data may be written to a cell by Fowler-Nordheim tunneling, also called “cold electron” tunneling. Cold electron tunneling is a quantum-mechanical effect allowing electrons to pass through, instead of over, the energy barrier at the interface of the device channel and the tunneling oxide. Because the electrons are passing through the barrier, this process requires less energy than hot electron injection, and can occur at a lower current density. In addition, use of Fowler-Nordheim tunneling for both programming and erasing enables operation voltages and power consumption to be reduced.
The cells are read by addressing the control gate and drain line of a cell with a positive voltage (e.g., 3 to 5 volts). If the floating gate is negatively charged (logical state “1”), the threshold voltage will be high and the cell device will not turn on when addressed. If the floating gate is uncharged (logical state “0”), the threshold voltage will be low, and the device channel will invert when addressed, causing a resulting current in the drain line that can be sensed by current sensing methods known in the art.
Erasure is accomplished by Fowler-Nordheim tunneling. A high voltage (e.g. 10 volts) is applied between the control gate and the source, causing electrons to leave the floating gate and tunnel through the tunneling oxide to the drain. Any individual cell or all cells may be simultaneously erased by applying an electrical pulse to any or all cells.
The easy reprogrammability, inherent short access time and non-volatility of the stored data make flash memory very attractive for many computer applications. Advancements in semiconductor fabrication technology have enabled the formation of denser and smaller memory arrays by decreasing the size of individual devices. Decreased device size has a cost, however, that is especially noticeable for split-gate transistors. Reduction in the size of the floating gate reduces the coupling ratio, resulting in slower operation speeds and degradation of programming and erase operations. In addition, devices with low coupling ratios require higher voltages for operation, an undesirable characteristic for many applications such as portable systems.
There is needed, therefore, a split-gate transistor exhibiting high coupling for use in device arrays such as flash memory arrays. A simple method of fabricating a high coupling split-gate transistor is also needed.
SUMMARY OF THE INVENTION
The present invention provides a split-gate transistor having high coupling due to the U-shaped configuration of the floating and control gates. Also provided is a method for its formation, in which a first polysilicon layer is formed on a substrate and then a plurality of nitride spacers are formed to divide the first polysilicon layer into individual floating gates. A plurality of polysilicon spacers are formed on top of the nitride spacers, which are then removed. Dielectric and control gate layers are then deposited. The resultant U-shaped configuration of the gates allows for a high coupling, thereby increasing the speed of the device while lowering the operation voltage and increasing the device density.
Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.
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Sandhu Gurtej S.
Sandhu Sukesh
Dickstein , Shapiro, Morin & Oshinsky, LLP
Jr. Carl Whitehead
Micro)n Technology, Inc.
Vockrodt Jeff
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