High burst rate write data paths for integrated circuit...

Details High burst rate write data paths for integrated circuit... High burst rate write data paths for integrated circuit...

2006-05-30

2006-05-30

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S219000, C365S220000, C365S221000

Reexamination Certificate

active

07054202

ABSTRACT:
Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

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Combined Search and Examination Report under Section 17 and 18(3), GB Application No. GB0412446.7, Oct. 29, 2004.

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