Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1998-05-29
2002-12-10
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S637000, C438S706000, C438S725000, C216S081000
Reexamination Certificate
active
06492276
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to oxygen containing plasma etchable layers within microelectronics fabrications. More particularly, the present invention relates to methods for forming residue free patterned oxygen containing plasma etched layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and microelectronics device and conductor element dimensions have decreased, it has become increasingly common within the art of microelectronics fabrication to employ interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor layers within microelectronics fabrications microelectronics dielectric layers formed of low dielectric constant dielectric materials. For the purposes of this disclosure, low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant of less than about 3.0. For comparison purposes, dielectric layers formed of conventional silicon oxide dielectric materials, silicon nitride dielectric materials or silicon oxynitride dielectric materials typically have dielectric constants in the range of from about 4.0 to about 5.0.
Microelectronics dielectric layers formed of low dielectric constant dielectric materials are desirable interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor layers within microelectronics fabrications since such dielectric layers formed from such low dielectric constant dielectric materials provide dielectric layers through which there may be fabricated microelectronics fabrications with enhanced microelectronics fabrication speed, attenuated patterned microelectronics conductor layer parasitic capacitance and attenuated patterned microelectronics conductor layer cross-talk.
Low dielectric constant dielectric materials which may be employed for forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications are typically materials with hydrogen and/or carbon content, such as but not limited to organic polymer spin-on-polymer dielectric materials (such as but not limited to polyimide organic polymer spin-on-polymer dielectric materials, poly (arylene ether) organic polymer spin-on-polymer dielectric materials and fluorinated poly (arylene ether) organic polymer spin-on-polymer dielectric materials), amorphous carbon dielectric materials (such as but not limited to amorphous carbon and fluorinated amorphous carbon), and silsesqiuoxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon silsesquioxane spin-on-glass (SOG) dielectric materials and carbon bonded fluorocarbon silsesquioxane spin-on-glass (SOG) dielectric materials).
While organic polymer spin-on-polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials are thus desirable within the art of microelectronics fabrication for forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications, organic polymer spin-on-polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials are not entirely without problems in forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications. In particular, it has been observed that when forming vias through carbon and fluorine containing oxygen containing plasma etchable fluorinated poly (arylene ether) organic polymer spin-on polymer dielectric materials to reach contact layers or contact regions formed within microelectronics fabrications while employing oxygen containing plasma etch methods as are disclosed within related co-pending and co-assigned patent application Ser. No. 09/086,772 filed May 27, 1998, issued as U.S. Pat. No. 6,019,906 on Feb. 1, 2000 titled Hard Masking Method for Forming Patterned Oxygen Containing Plasma Etchable Layer, there is often formed upon the sidewalls of the vias residue layers, which are presumably fluoropolymer residue layers. Such residue layers are undesirable when formed upon the sidewalls of vias formed through carbon and fluorine containing dielectric layers such as but not limited to fluorinated poly (arylene ether) organic polymer spin-on-polymer dielectric layers since their presence often precludes forming within those vias fully functional or reliable conductor stud layers.
It is thus towards the goal of forming within advanced microelectronics fabrications while employing oxygen containing plasma etch methods patterned low dielectric constant microelectronics dielectric layers formed from oxygen containing plasma etchable dielectric materials formed of carbon and fluorine containing materials, with attenuated residue formation upon the sidewalls of those patterned low dielectric constant microelectronics dielectric layers, that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards forming within advanced microelectronics fabrications while employing oxygen containing plasma etch methods patterned microelectronics layers (not necessarily patterned microelectronics dielectric layers) formed of oxygen containing plasma etchable materials formed of carbon and fluorine containing materials, with attenuated residue formation upon the sidewalls of those patterned microelectronics layers.
Consistent with that which is cited within related co-pending and co-assigned Ser. No. 09/086,772 filed May 27, 1998, issued as U.S. Pat. No. 6,019,906 on Feb. 1, 2000 various photolithographic and etch methods have been disclosed in the art of microelectronics fabrication for forming patterned microelectronics layers within microelectronics fabrications.
For example, Liu in ULSI Technology, C. Y. Chang et al., eds., McGraw-Hill (1996), pp. 446-47, discloses in general various methods for forming within integrated circuit microelectronics fabrications bordered and borderless stacked patterned conductor contact layers. Disclosed are both damascene and non-damascene methods for forming the bordered and borderless stacked patterned conductor contact layers.
Similarly, Korczynski, in “Low-k dielectric integration cost modelling,” Solid State Technology, October 1997, pp. 123-28, discloses in general various methods for forming patterned low dielectric constant dielectric layers interposed between the patterns of patterned conductor interconnection layers within microelectronics fabrications. Disclosed are standard patterned conductor metal interconnection formation and isolation methods and dual damascene patterned conductor metal interconnection formation and isolation methods.
In addition, Lin et al., in U.S. Pat. No. 5,246,883, discloses a method for forming a contact via structure through at least one dielectric layer within an integrated circuit microelectronics fabrication. The method employs at least the one dielectric layer having formed thereover a first buffer layer which in turn has formed thereupon a second buffer layer, where the second buffer layer has a higher isotropic etch rate in an isotropic etch method than the first buffer layer. By employing the isotropic etch method for etching the second buffer layer and at least a portion of the first buffer layer, followed by an anisotropic etch method for etching any remainder of the first buffer layer and at least the one dielectric layer, the taper of the sidewall of a via formed through at least the second buffer layer, the first buffer layer and the dielectric layer may be controlled.
Further, Moslehi, in U.S. Pat. No. 5,460,69
Ackerman Stephen B.
Nguyen Tuan H.
Pham Thanhha
Saile George O.
Stanton Stephen G.
LandOfFree
Hard masking method for forming residue free oxygen... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hard masking method for forming residue free oxygen..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hard masking method for forming residue free oxygen... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2944116