Halo structure for CMOS transistors and method of...

Details Halo structure for CMOS transistors and method of... Halo structure for CMOS transistors and method of...

2000-01-12

2001-07-10

Fabmy Jr., Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000, C438S291000, C438S307000

Reexamination Certificate

active

06258645

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and particularly to the manufacture of CMOS field-effect transistors (FETs) having halo structures.
DESCRIPTION OF THE INVENTION
As the minimum feature size in semiconductor integrated circuits shrinks, the distance between the source and drain regions becomes smaller. The reduced spacing between the source and drain regions for the field-effect transistors (FETs) results in short channel effects such as punch-through, reduced source-to-drain breakdown voltage, reduced threshold voltage (V
T
), and increased sub-threshold swing. To relieve the short channel effects, the semiconductor industry is constantly optimizing the fabrication processes for MOSFET devices. Current trends in VLSI fabrication of CMOS devices are toward reducing the junction depth of the source/drain regions because shallow junctions reduce the encroachment of the source/drain depletion regions into the channel.
Another approach introduces a punch-through implant, which increases the concentration of channel type impurities beneath the channel where breakdown typically occurs. The punch-through implant is below the channel so that the active channel impurity concentration is substantially unaffected. The increased background impurity concentration effectively reduces the depletion zone width, thereby increasing the breakdown voltage.
Advances in semiconductor processing technology have now reduced channel lengths to well below 0.25 &mgr;m. At these sizes, any loss of effective channel length can be costly in terms of lowering the breakdown voltage of a transistor. Accordingly, limiting the lateral diffusion of the source/drain impurities is increasingly important.
A halo implant, also called a “pocket implant”, can limit the lateral diffusion of the source and drain impurities. The halo implant implants impurities having a conductivity type opposite to that of the source and drain. Usually, the halo implant comes after defining the gate and before the source/drain diffusion. Due to the masking effect, the halo implant typically exhibits a peak impurity concentration near the source/drain regions. To impede vertical diffusion of source/drain impurities, the implant energy for the halo implant should be carefully chosen so that the halo depth away from the peak is greater than the depth of the source/drain implant.
U.S. Pat. Nos. 5,747,855 and 5,534,449 describe halo implant methods that form halo structures. CMOS processes usually perform the halo implants separately for the PMOS and NMOS devices. This is because the halo implant for the PMOS devices use N-type impurities such as phosphorus and arsenic, but the halo implant for the NMOS devices use the P-type impurities such as boron and BF
2
. Accordingly, U.S. Pat. Nos. 5,747,855 and 5,534,449 employ an additional photolithography process to mask the PMOS devices during the halo implant for the NMOS devices. This additional masking step increases the complexity of the fabrication process and increases the cost of the fabricated semiconductor chips. If, however, the masking step is skipped and the halo implant for the NMOS transistor, for example, is performed simultaneously over the whole wafer, the halo implant destroys the optimization of the PMOS transistor.
Furthermore, if a cell transistor in a memory cell array is exposed to the boron halo implant for the NMOS devices, the leakage current and the junction capacitance of the cell transistor will tend to increase.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, a semiconductor device and a fabrication method thereof simplify application a halo implant to the CMOS process. The fabrication method applies a uniform halo implant to a CMOS structure without destroying the optimization of transistors or employing an additional photo-mask for the halo implant process. In particular, the halo implant applies to a CMOS process forming a DRAM memory without destroying the structure of the cell transistor in a DRAM memory cell.
In accordance with a broad aspect of the present invention, a semiconductor device fabrication process performs a halo implant with a projected range (e.g., depth and impurity concentration) within a projected range of a LIF or counter-doping implant defined during formation of a well of the opposite conductivity type. As a result, impurities in the well compensate for impurities from the halo implant, and a CMOS process can form a halo structure without requiring an additional lithographic masking process.


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patent: 6159815 (2000-12-01), Lustig et al.
patent: 6174759 (2001-01-01), Verhaar et al.

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