Guard wall to reduce delamination effects within a semiconductor

Details Guard wall to reduce delamination effects within a semiconductor Guard wall to reduce delamination effects within a semiconductor

1993-08-26

1999-11-16

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257484, 257605, 257629, 257630, H01L 2131

Patent

active

059863153

ABSTRACT:
A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.

REFERENCES:
patent: 4096622 (1978-06-01), MacIver
patent: 4137109 (1979-01-01), Aiken et al.
patent: 4261095 (1981-04-01), Dreves et al.
patent: 4317274 (1982-03-01), Yasunari
patent: 4375597 (1983-03-01), Kosonocky
patent: 4414737 (1983-11-01), Menjo et al.
patent: 4507853 (1985-04-01), McDavid
patent: 4549914 (1985-10-01), Oh
patent: 4641420 (1987-02-01), Lee
patent: 4656732 (1987-04-01), Teng et al.
patent: 4691435 (1987-09-01), Anantha et al.
patent: 4722910 (1988-02-01), Yasaitis
Full English Translation of Japan Kokai 64-69051 as per Uspto.

Affiliated with

Also associated with

Rating

Guard wall to reduce delamination effects within a semiconductor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Guard wall to reduce delamination effects within a semiconductor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Guard wall to reduce delamination effects within a semiconductor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1328002