Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2002-02-26
2003-10-07
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S124000, C438S112000, C438S127000
Reexamination Certificate
active
06630373
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to an improved design of a semiconductor die paddle.
(2) Description of the Prior Art
The semiconductor industry has for many years achieved improvements in the performance of semiconductor devices by device miniaturization and by increasing the device packaging density. For this purpose, metal interconnects can readily be provided by metal lines that are embedded in layers of dielectric, using vias to provide electrical connections between overlying layers of interconnect lines. Interconnect lines must thereby be connected in such a manner that optimum performance can be realized for the completed package. Good planarity must also be maintained between adjacent layers of interconnect lines because metal interconnect lines are typically narrow in width and thick in a vertical direction (in the range of 5 to 10 microns thick) and must be patterned with microlithography. Patterned layers must therefore be substantially flat and smooth (i.e. have good planarity) so that these layers can serve as a base for the next layer.
One of the original approaches that has been used to create surface mounted, high pin-count integrated circuit packages has been the use of the Quad Flat Pack (QFP) with various pin configurations. For the QFP, closely spaced leads along the four edges of the flat package are used for making electrical connections from where the electrical connections are distributed to the surrounding circuitry. The QFP has found to be cost-effective for semiconductor devices where the device I/O pin count does not exceed 200. To circumvent this limitation, a new package, a Ball Grid Array (BGA) package has been introduced. For the BGA package, the electrical contact points are distributed over the entire bottom surface of the package. More contact points with greater spacing between the contact points can therefore be allocated across the BGA package than was the case with the QFP.
Flip Chip packages have in general been used to accommodate increased I/O count combined with increased high requirements for high performance Integrated Circuits. Flip chip technology fabricates bumps (typically Pb/Sn solder) on aluminum pads and interconnects the bumps directly to the packaging media, which are usually ceramic or plastic based substrates. The flip-chip is bonded face down to the package through the shortest paths. This approach can be applied to single-chip packaging and to higher levels of integrated packaging (in which the packages are larger) and to more sophisticated packaging media that accommodate several chips to form larger functional units.
For the packaging of semiconductor devices, the packages in which the devices are contained provide protection of the device from environmental influences such as mechanical damage or damage caused by moisture affecting exposed surfaces of the device. Part of the package design includes the design of electrically conductive interfaces that enable the device to be electrically interconnected with surrounding circuitry. Increased device density has not only created new demands for input/output connections of the device but has also caused considerable more thermal energy to be expanded per cubic volume content of the device. In many of the semiconductor device packages, the device is mounted in close physical proximity to a heat sink. This is combined with methods, such as connections of low resistance to thermal heat conductivity, that are implemented as part of the package.
U.S. Pat. No. 6,300,673 (Hoffman et al.) shows a die attach paddle and ground plane for a package.
U.S. Pat. No. 6,284,571 B1 (Corisis et al.) describes a structure for a die attach paddle and ground plane for a package.
U.S. Pat. No. 6,096,163, (Wensel) shows a process for adhesives to a leadframe.
U.S. Pat. No. 5,434,750 (Rostoker) shows another leadframe design.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide improved bond reliability for wire bond interfaces of a semiconductor package.
Another objective of the invention is to reduce stress related problems in a semiconductor package.
Yet another objective of the invention is to reduce the impact of mismatched Coefficients of Thermal Expansion (CTE) between components of a semiconductor device package.
In accordance with the objectives of the invention a new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground plane is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.
REFERENCES:
patent: 5434750 (1995-07-01), Rostoker et al.
patent: 6008073 (1999-12-01), King et al.
patent: 6096163 (2000-08-01), Wensel
patent: 6284571 (2001-09-01), Corisis et al.
patent: 6300673 (2001-10-01), Hoffman et al.
Han Byung Joon
Punzalan Jeffrey D.
Tan Hien Boon
Yee Jae Hak
Zheng Zheng
Ackerman Stephen B.
Saile George O.
ST Assembly Test Service Ltd.
Talbott David L.
Thai Luan
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