Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-03-09
2004-07-13
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
06763488
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional Scan-BIST architectures into low power Scan-BIST architectures.
2. Description of the Related Art
FIG. 1
illustrates a conventional Scan-BIST architecture that a circuit
100
can be configured into during test. In the normal functional configuration, circuit
100
may be a functional sub-circuit within IC, but in test configuration it appears as shown in FIG.
1
. The Scan-BIST architecture is typically realized within a sub-circuit of an IC, such as an intellectual property core DSP or CPU sub-circuit. The Scan-BIST architecture includes a generator circuit
102
, compactor circuit
106
, scan path circuit
104
, logic circuitry to be tested
108
, and controller circuit
110
. Generator
102
operates to produce and output serial test stimulus patterns to scan path
104
via path
118
. Compactor
106
operates to input and compress serial test response patterns from scan path
104
via path
120
. Scan path
104
operates, in addition to its serial input and output modes, to output parallel test stimulus patterns to logic
108
via path
122
, and input parallel response patterns from logic
108
via path
124
. Controller
110
operates to produce and output the control required to operate generator
102
via path
112
, scan path
104
via path
114
, and compactor
106
via path
116
. Generator
102
may be designed using any suitable type of circuit for producing stimulus patterns, such as linear feedback shift registers. Compactor
106
may be designed using any suitable type of circuit for compacting response patterns into signatures, such as signature analysis registers. Controller
110
may be designed using any suitable type of controller or state machine designed to autonomously operate generator
102
, scan path
104
, and compactor
106
during test.
The circuit of
FIG. 1
may be configured into the illustrated Scan-BIST architecture and enabled to start a test operation in response to a variety of methods, including; (1) in response to power up of the circuit, (2) in response to manipulation of external inputs to the circuit, or (3) in response to data loaded into a register, such as the IEEE 1149.1 TAP instruction register.
FIG. 2
illustrates an example of a conventional scan cell that could be used in scan path
104
. (Note: The optional scan cell multiplexer
218
and connection paths
220
and
224
, shown in dotted line, will not be discussed at this time, but will be discussed later in regard to FIGS.
7
and
8
.) The scan cell consists of a D-FF
204
and a multiplexer
202
. During normal configuration of the circuit
100
, multiplexer
202
and D-FF
204
receive control inputs SCANENA
210
and SCANCK
212
to input and output functional data to logic
108
via paths
206
and
216
, respectively. In the normal configuration, the SCANCK to D-FF
204
is typically a functional clock, and the SCANENA signal is set such that the D-FF always clocks in functional data from logic
108
via path
206
. During the test configuration of
FIG. 2
, multiplexer
202
and D-FF
204
receive control inputs SCANENA
210
and SCANCK
212
to capture test response data from logic
108
via path
206
, shift data from scan input path
208
to scan output path
214
, and apply test stimulus data to logic
108
via path
216
. In the test configuration, the SCANCK to D-FF
204
is the test clock and the SCANENA signal is operated to allow capturing of response data from logic
108
and shifting of data from scan input
208
to scan output
214
. During test configuration, SCANENA is controlled by controller
110
. SCANCK may also be controlled by the controller, or it may be controlled by another source, for example the functional clock source. For the purpose of simplifying the operational description, it will be assumed that the SCANCK is controlled by the controller.
The scan inputs
208
and scan outputs
214
of multiple scan cells are connected to form the serial scan path
104
. The stimulus path
216
and response path
206
of multiple scan cells in scan path
104
form the stimulus bussing path
122
and response bussing path
124
, respectively, between scan path
104
and logic
108
. From this scan cell description, it is seen that the D-FF is shared between being used in the normal functional configuration and the test configuration. During scan operations through scan path
104
, the stimulus outputs
216
from each scan cell ripple, since the stimulus
216
path is connected to the scan output path
214
. This ripple causes all the inputs to logic
108
to actively change state during scan operations. Rippling the inputs to logic
108
causes power to be consumed by the interconnect and gating capacitance in logic
108
.
FIG. 3
illustrates a simplified example of the operation
300
of controller
110
during test. Initially the controller will be in an idle
302
or non-operational state. In response to a start test operation input, for example using one of the methods mentioned above, the controller transitions from the idle state to the operate state
304
. In the operate state, the controller issues control to the generator, scan path, and compactor. In response to the control, the generator begins producing stimulus data to the scan path, the scan path begins accepting the stimulus data and outputting response data, and the compactor begins inputting and compressing the response data from the scan path. The controller remains in the operate state until the scan path has been filled with stimulus data and emptied of response data. From the operate state, the controller passes through the capture state
306
to load response data from the logic
108
, then re-enters the operate state. Since the initial response data from the scan path may be unknown, unless for example the scan path is initialized at the beginning of the test, the response data input to the compactor may be delayed or masked off until after the controller has passed through the capture state
206
a first time. The process of entering the operate state to load stimulus into the scan path and empty response from the scan path, then passing through the capture state to load new response data repeats until the end of test. At end of test the controller re-enters the idle state. Upon re-entering the idle state, the controller may output an end of test (EOT) signal
111
to indicate test completion. The compactor may be designed to include an expected response signature value that is compared against the signature obtained from the test. If so, the compactor will typically output a PASS/FAIL signal
117
at end of test to indicate whether the signature taken matched the expected signature. The use of EOT and PASS/FAIL signals are assumed in subsequent Figures, but will not be shown.
FIG. 4
illustrates a timing example of how controller
110
outputs SCANENA and SCANCK signals to scan path
104
during scan operations. In this example, a high to low transition on SCANENA, at time
406
, in combination with SCANCKs occurring during time interval
402
, causes stimulus data from generator
102
to be input to the scan path while response data is output to compactor
106
. A low to high transition on SCANENA, at time
408
, in combination with a SCANCK at time
404
, causes response data from logic
108
to be loaded into the scan path. Time interval
402
relates to operate state
304
and time interval
404
relates to capture state
306
of FIG.
3
. As seen in the timing and operation diagrams of
FIGS. 3 and 4
, the time interval sequences
404
(i.e. state
306
) and
402
(i.e. state
304
) cycle a sufficient number of times during test to input all stimulus to and obtain all response from logic
108
.
From the Scan-BIST architecture described in regard to
FIGS. 1
,
2
,
3
, and
4
it is seen that the stimulus
122
outputs ripple the inputs to logic
108
as data shi
Bassuk Lawrence J.
Brady W. James
Britt Cynthia
De'cady Albert
Telecky , Jr. Frederick J.
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