Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-10-11
2004-11-02
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S706000
Reexamination Certificate
active
06812147
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to applying gas cluster ion beams (GCIB) to improve the quality of electrical interconnections in integrated circuitry, and, more particularly to improving electrical interconnections by etching and/or cleaning the bottoms of interconnect vias between integrated circuit interconnect layers in circuits employing the dual damascene process, or the like, prior to forming the interconnecting via plug.
The use of a gas cluster ion beam for etching or cleaning planar material surfaces is known (see for example, U.S. Pat. No. 5,814,194, Deguchi et al.) in the art. For purposes of this discussion, gas clusters are nano-sized aggregates of materials that are gaseous under conditions of standard temperature and pressure. Such clusters typically consist of aggregates of from a few to several thousand molecules loosely bound to form the cluster. The clusters can be ionized by electron bombardment or other means, permitting them to be formed into directed beams of known and controllable energy. The larger sized clusters are often the most useful because of their ability to carry substantial energy per cluster ion, while yet having only modest energy per molecule. The clusters disintegrate on impact, with each individual molecule carrying only a small fraction of the total cluster energy. Consequently the impact effects of large clusters are substantial, but are limited to a very shallow surface region. This makes ion clusters effective for a variety of surface modification processes, without the tendency to produce deeper subsurface damage characteristic of monomer ion beam processing.
Means for creation of and acceleration of such GCIBs are described in the reference (U.S. Pat. No. 5,814,194) previously cited. Presently available ion cluster sources produce clusters ions having a wide distribution of sizes, n (where n=the number of molecules in each cluster—in the case of monatomic gases like argon, an atom of the monatomic gas will be referred to as a molecule and an ionized atom of such a monatomic gas will be referred to as a molecular ion—or simply a monomer ion—throughout this discussion).
In the semiconductor industry, increasing circuit density drives progress toward smaller and smaller dimensions and larger numbers of transistors placed in an individual device. The challenges to interconnect these transistors becomes increasingly difficult. Some of the problems faced with denser interconnections are increased heat dissipation, greater power consumption, and longer signal delays resulting from higher resistance in the interconnects. Moving to the use of lower resistivity metals for the interconnections helps to alleviate these problems, and the dual damascene Cu interconnect scheme is becoming favored. However, in common modern interconnect structures a diffusion barrier material must be employed to encapsulate the metal conductor to prevent diffusion of the conductor metal atoms so as to avoid undesired contamination of the semiconductor materials. Typical barrier materials used are thin films of materials such as Ta, TiN, TaN, etc., which have significantly higher electrical resistivities than the Al or Cu used as the interconnect metal. Dielectric materials like SiC and SiN also make effective diffusion barriers and have advantages but have not so far found wide acceptance because they have much higher electrical resistance and do not provide low resistance electrical continuity at the bottoms of electrical interconnect vias. Usually, cylindrical vias form the connections between interconnect metal layers, and barrier material films are used inside the vias. The barrier materials must first be deposited in such a way as to form a continuous layer on the sidewalls of the via. Typically this results in an additional amount also deposited at the bottom of the contact (bottom or base of the via). This film at the bottom of the contact is unnecessary as a diffusion barrier since the adjacent material is the interconnect metal, and unfortunately contributes an increased resistivity obstruction in the electrical current path. The interface resistance between the interconnect metal and the barrier material also exacerbates this problem. The Semiconductor Industry Association's
International Technology Roadmap for Semiconductors
(ITRS 2000) projects that barrier/cladding thickness must be decreased to from 13 nm to 10 nm by 2005 and to 0 nm by 2008 in order to meet industry goals.
Another significant source of high contact resistance is residue of materials from previous process steps in the manufacturing of the interconnect structures that tend to be trapped or otherwise remain in the bottom of the contact via structures. These residues generally consist of high resistivity materials such as organic compounds from photo-resists, and by-products of etching of other layers in the film stack. The removal of this contamination layer at the bottom of a contact structure is another significant means for improvement in IC performance.
In modern interconnect technology, via holes are etched through the inter-metal dielectric layer between interconnect layers, using a mask. After etching, the bottom of the vias have residual byproducts (such as for example, SiN and CuO in a dual damascene process) that can adversely affect via interconnect resistance. It is problematic to effectively get etchants to the bottoms of the interconnect vias. Plasma etching or cleaning technologies operate in the range of pressures greater than 10
−3
Torr. At such pressures the mean free path of the ion is short (less than about 5 cm for Ar at 10
−3
Torr) and make many collisions that result in poor etching directionality. Thus the reactive ions tend to attack the interconnect via sidewalls and can undesirably reduce the sidewall barrier material thickness. This increases the risk of a breach in the barrier. It is also very difficult to get reacted material evacuated from the bottom of the contact. After the cleaning step, a barrier material is deposited and then the via is filled with the plug material (for Al interconnects) or, for Cu interconnects, a seed Cu layer is deposited and then the via is then filled with a Cu plug. Any residues can dramatically degrade the interconnect via characteristics.
GCIBs having sufficient flux density to clean or etch planar surfaces or surfaces having modest deviations from planarity are readily generated with existing technology. Similarly, more conventional monomer ion beams capable of etching or milling or cleaning planar or near-planar surfaces are also readily generated. When such beams are used to clean or etch surfaces, the cleaning or etching generally results from a sputtering process or in the case where a reactive ion species is employed, reactions of the ions with the surface can work in combination with a sputtering process. Because of the large aspect ratios of interconnect vias it has not been practical to clean or etch the bottoms of interconnect vias without undesirable effects on the sidewalls of the vias. Directed beams of conventional monomer ions are not readily produced with high flux densities necessary for practical cleaning or etching rates while simultaneously having a high degree of directionality (low beam emittance and low beam divergence). Energetic monomer ions striking a surface at a grazing angle tend to have a higher sputtering rate much higher than they do when they strike a surface at normal or near-normal incidence. Accordingly, when such ions are directed down an interconnect via hole, sputtering of the sidewalls tends to proceed at a higher rate than sputtering of the bottom.
It is therefore an object of this invention to provide a method to effectively and efficiently clean the bottoms of interconnect vias without significantly degrading the integrity of the barrier material film on the interconnect via sidewalls.
It is also an object of this invention to provide a method to effectively and efficiently clean or etch the bottoms of interconnect vias with
Hautala John J.
Skinner Wesley J.
Cohen Jerry
Epion Corporation
Erlich Jacob N.
Geyer Scott B.
Perkins Smith & Cohen LLP
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