Gate etch process for a high-voltage FET

Details Gate etch process for a high-voltage FET Gate etch process for a high-voltage FET

2008-03-15

2009-02-24

Le, Thao X (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C257S328000

Reexamination Certificate

active

07494875

ABSTRACT:
A method, in one embodiment, includes etching first and second dielectric regions in a substantially isotropic manner through first and second openings of a mask layer to create first and second trenches. The first and second dielectric regions are disposed on opposite sides of a mesa of semiconductor material, the mesa having first and second sidewalls that respectively adjoin the first and second dielectric regions. The first and second dielectric regions in the first and second trenches are then etched in a substantially isotropic manner to expose the first and second sidewalls. A gate oxide is formed on the first and second sidewalls of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

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