Gate electrode for a semiconductor fin device

Details Gate electrode for a semiconductor fin device Gate electrode for a semiconductor fin device

2007-02-13

2007-02-13

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S287000, C257SE21442, C257SE29275, C257SE29299

Reexamination Certificate

active

10825872

ABSTRACT:
A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction and activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.

REFERENCES:
patent: 6252284 (2001-06-01), Muller et al.
patent: 6391695 (2002-05-01), Yu
patent: 6391782 (2002-05-01), Yu
patent: 6413802 (2002-07-01), Hu et al.
patent: 6432829 (2002-08-01), Muller et al.
patent: 6451656 (2002-09-01), Yu et al.
patent: 6458662 (2002-10-01), Yu
patent: 6492212 (2002-12-01), Ieong et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6657252 (2003-12-01), Fried et al.
patent: 6767793 (2004-07-01), Clark et al.
patent: 6794718 (2004-09-01), Nowak et al.
patent: 6803631 (2004-10-01), Dakshina-Murthy et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
X. Huang et al., “Sub-50 nm P-Channel FinFet”, IEEE Transactions On Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
F.-L. Yang et al., “35nm CMOS FinFETs”, 2002 Symposium On VLSI Technology Digest of Technical Papers, Jun. 2002, pp. 104-105.
H.-S. P. Wong, “Beyond the conventional transistor”, IBM J. Research and Development, vol. 46, No. 2/3, Mar./May 2002, pp. 133-168.
R. Chau et al., “Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate” (Invited Paper), 2002 International Conference on Solid State Devices and Materials, Nagoya, Japan, Sep. 2002, pp. 68-69.
F.-L. Yang et al., “25 nm CMOS Omega FETs”, International Electron Device Meeting, Dig. Technical Papers, Dec. 2002, pp. 255-258.
J. P. Colinge et al., “Silicon-On-Insulator ‘Gate-All-Around Device’”, International electron Device Meeting, Dig. Technical Papers, Dec. 1990, pp. 595-598.
E. Leobanddung et al., “Wire-channel and wrap-around-gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects”, J. Vacuum Science and Technology B, vol. 15, No. 6, Nov./Dec. 1997, pp. 2791-2794.

Affiliated with

Also associated with

Rating

Gate electrode for a semiconductor fin device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate electrode for a semiconductor fin device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate electrode for a semiconductor fin device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3890816