Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-05-24
2011-05-24
Pizarro, Marcos D. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C257S369000, C257SE21632
Reexamination Certificate
active
07947549
ABSTRACT:
CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.
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Chudzik Michael P
Jha Rashmi
Krishnan Siddarth A
Moumen Naim
Narayanan Vijay
International Business Machines - Corporation
Montalvo Eva Yan
Percello Louis J.
Pizarro Marcos D.
Sai-Halasz George
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