Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2002-04-23
2004-05-11
Zarneke, David A. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C029S832000, C029S841000, C361S783000
Reexamination Certificate
active
06734372
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microelectronic packaging and, more particularly, to molding an integrated circuit device.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled circuits are used in a wide variety of applications. Such applications include personal computers, control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device coupled to the microprocessor.
Devices in these types of circuits are typically formed on a semiconductor die and placed in what is known in the art as a package. Many electrical circuits are packaged for surface mounting, and Fine-Pitch Surface Mount Technology (FPT) and Pin Grid Array (PGA) technology are well developed areas of this type packaging technology. In addition, an emerging packaging method has been developed using Ball Grid Array (BGA) technology.
A BGA semiconductor package generally includes a semiconductor chip mounted on the upper surface of a substrate. The semiconductor chip may be electrically coupled to the substrate by bonding wires or conductive paste. The substrate contains conductive routing which allows the signals to pass from the semiconductor chip on the upper surface of the substrate, through the substrate, and to pads on the underside of the substrate. A plurality of solder balls are deposited and electrically coupled to the pads on the underside of the substrate to be used as input/output terminals for electrically connecting the substrate to a printed circuit board (PCB) or other external device.
The packaging of electrical circuits is a key element in the technological development of any device containing electrical components. A single integrated circuit die is typically encapsulated within a sealed package to be mounted on a PCB or another suitable apparatus for incorporation into a system. The integrated circuit die is generally encapsulated within a molding compound to protect the die from external contamination or physical damage. Because the integrated circuit die is generally encapsulated, the encapsulated integrated circuit package also provides a system of interconnects for electrically coupling the integrated circuit die to a PCB or other external device.
Three common techniques for mounting an integrated circuit die on a substrate include Chip-on-Board (COB), Board-on-Chip (BOC), and Flip-Chip (F/C). In a COB package, the integrated circuit die may be attached to the substrate “face-up.” That is to say that the side of integrated circuit die containing the bond pads for wire bonding the integrated circuit die to the substrate is left exposed. This side is often referred to as the upper surface of the die. The backside of the integrated circuit die not containing the bond pads is adhered to the substrate. In this type of package, bond wires are attached from the upper surface of the integrated circuit die and to pads on the upper surface of the substrate to electrically couple the integrated circuit die to the substrate. The substrate contains electrical routing which routes the signals from the upper surface of the substrate to the underside of the substrate.
Alternately, the integrated circuit die may be mounted on the substrate “face-down,” to create a BOC. In this instance, the substrate typically contains a slot. Since the integrated circuit die is mounted face down, the bond pads on the upper surface of the die are arranged to correlate with the slot opening in the substrate. Bond wires are attached from the bond pads on the die, through the slot in the substrate, and to the underside of the substrate. The substrate contains electrical routing to distribute electrical signals along the backside of the substrate.
For F/C packages, the integrated circuit die is mounted on the substrate face-down as in the BOC package. For a F/C package, bond wires are not used to electrically couple the integrated circuit die to the substrate. Instead, solder bumps located on the face of the integrated circuit die are aligned with conductive pads on the upper surface of the substrate. The solder bumps may be reflowed to electrically couple the integrated circuit die to the substrate. The substrate contains electrical routing to distribute electrical signals from the die along the backside of the substrate.
Regardless of whether COB, BOC or F/C mounting techniques are used, the package is generally encapsulated in a molding compound to protect the integrated circuit device and bond wires from external elements such as moisture, dust, or impact. A transfer molding system or an injection molding system may be used to dispose a molding compound about the package. In an injection molding system, a package is mounted into a system and a molding compound is injected through a runner and onto the package via a gate area. Once the molding process is complete, the package is removed from the system by breaking the molding compound along the runner away from the package at the gate area. However, breaking the compound at the gate area often creates separation problems between the molding compound and the substrate. To mitigate this effect, a release material may be disposed on the surface of the substrate at the gate area. While the release material may facilitate removal of the package from the molding compound, the break area is often left rough as a result of lifting of the release material. This often results in rejection or failure of the package at inspection or test.
The present invention may address one or more of the problems set forth above.
SUMMARY OF THE INVENTION
Certain aspects commensurate in scope with the disclosed embodiments are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In one embodiment of the present invention, there is provided a system having a processor and a memory package operatively coupled to the processor. The memory package has a memory device attached to a substrate, and a molding compound disposed on the substrate. The substrate also has a relief region.
In another embodiment of the present invention, there is provided an integrated circuit package having an integrated circuit device coupled to a substrate, and a molding compound disposed on the substrate. The substrate also has a relief region.
In still another embodiment of the present invention, there is provided a method of building an integrated circuit package comprising the acts of: providing a substrate; disposing a relief region onto the surface of the substrate; disposing an integrated circuit device onto the substrate; and disposing a molding compound about the integrated circuit device.
In yet another embodiment of the present invention, there is provided a method of building an integrated circuit package comprising the acts of: providing a substrate having a relief area on a surface of the substrate; disposing an integrated circuit device onto the substrate; and disposing a molding compound about the integrated circuit device.
REFERENCES:
patent: 5629566 (1997-05-01), Doi et al.
patent: 5804881 (1998-09-01), Wille et al.
patent: 5818698 (1998-10-01), Corisis
patent: 6160713 (2000-12-01), Floyd et al.
patent: 6
James Stephen L.
Rumsey Brad D.
Wensel Richard W.
Fletcher Yoder
Norris Jeremy
Zarneke David A.
LandOfFree
Gate area relief strip for a molded I/C package does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Gate area relief strip for a molded I/C package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate area relief strip for a molded I/C package will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3223522