Fully asynchronous interface with programmable metastability set

Details Fully asynchronous interface with programmable metastability set Fully asynchronous interface with programmable metastability set

1995-01-19

1997-01-28

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Metastable state prevention

327141, 327154, 327163, H03K 1900, H03K 5135

Patent

active

055981135

ABSTRACT:
A fully asynchronous parallel synchronizer having staged write and read enables and an asynchronous interface for same. The asynchronous interface can be used to interconnect two processor systems (e.g., within a multiple processor system or a parallel processor system). The parallel programmable synchronizer contains n latches coupled in parallel having n individual enable lines having staggered enable signals. The latches are coupled such that they output to a multiplexing circuit that also receives individual staggered read enable signals which are based on the write enable signals. According to the parallel programmable synchronizer, data is written into a particular latch in clock cycle (i) just after other data was read from the same particular latch in a just prior clock cycle (i-1). While the synchronizer contains n latches, the number of latches used, x, for any particular embodiment is programmable and the enable signals adjust to accommodate the number of latches selected. The settling time for the synchronizer is therefore programmable while the synchronizer also provides a maximum throughput frequency (sampling rate). A novel empty flag generation is also described.

REFERENCES:
patent: 4891808 (1990-01-01), Williams
patent: 5014226 (1991-05-01), Horstmann et al.
patent: 5056120 (1991-10-01), Taniguchi et al.
patent: 5321368 (1994-06-01), Hoelzle et al.

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