FPGA memory element programmably triggered on both clock edges

Details FPGA memory element programmably triggered on both clock edges FPGA memory element programmably triggered on both clock edges

1997-07-09

1998-12-01

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523008, 36518902, G11C 700

Patent

active

058448446

ABSTRACT:
A programmable memory element clocks in new data on both rising and falling edges of the clock, thereby optionally operating at twice the frequency of the distributed clock. The circuit according to the invention comprises two latches, one rising edge triggered and one falling edge triggered. One of these latches, each time the clock changes state, latches in a new value. When configured as a dual-edge flip-flop, the output of the inactive latch is fed forward to drive the output of the memory element. In one embodiment, the outputs of the two latches are multiplexed together and the clock selects the active output. According to a first embodiment of the invention, the memory element is used in an FPGA and can be programmed to function as either a latch or a dual-edge flip-flop. A second embodiment of the invention comprises a third latch. Based on the contents of a configuration memory cell, two of the three latches are selected to form a flip-flop. One such flip-flop is dual-edge, the other is single-edge. Further embodiments incorporate programmable variations of latches and flip-flops responsive to either or both clock edges.

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