Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-09-25
2007-09-25
Tran, Minh-Loan (Department: 2826)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C228S180220, C228S253000, C174S265000, C257SE23023
Reexamination Certificate
active
10905013
ABSTRACT:
Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.
REFERENCES:
patent: 4412642 (1983-11-01), Fisher, Jr.
patent: 5211328 (1993-05-01), Ameen et al.
patent: 5718367 (1998-02-01), Covell et al.
patent: 5775569 (1998-07-01), Berger et al.
patent: 6029882 (2000-02-01), Bolde et al.
patent: 6133633 (2000-10-01), Berger et al.
patent: 6149122 (2000-11-01), Berger et al.
patent: 6294745 (2001-09-01), Gruber
patent: 6329631 (2001-12-01), Yueh
patent: 6340630 (2002-01-01), Berger et al.
patent: 6426241 (2002-07-01), Cordes et al.
patent: 6454159 (2002-09-01), Takushima
patent: 6461136 (2002-10-01), Gruber et al.
Ames Laboratory New Release, “Ductile Intermetallic Compounds Discovered: Ames Laboratory Researchers Indentify Non-Brittle Intermetallics,” Midwest Forensics Resource Center, http://www.external.ameslab.gov
ews/release/2003rel/ductile.htm , Sep. 15, 2003, pp. 1-2.
IBM Research, “Injection Molded Soldering,” http://www.research.ibm.com/ims/Oct. 15, 2004, pp. 1-3.
Geheim, G. et al, “Deep RIE Process for Silicon Carbide Power Electronics and MEMS,” Materials Research Society Symposium Proceedings, vol. 622, 2000, pp. 1-6.
“High Aspect Ratio Etching,” http://www.protron-mikrotechnik.de/technology/technology—ase—e—2.htm Nov. 3, 2004, pp. 1-2.
“Central Fabrication Facility: Deep Silicon RIE,” NMRC, http://www.nmrc.ie/facilities/cff/mic—sys—rie.html, Sep. 29, 2004, pp. 1-2.
Groves Robert A.
Gruber Peter A.
Petrarca Kevin S.
Volant Richard P.
Walker George F.
Hoffman Warnick & D'Alessandro LLC
International Business Machines - Corporation
Jaklitsch Lisa U.
Tran Minh-Loan
LandOfFree
Forming of high aspect ratio conductive structure using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Forming of high aspect ratio conductive structure using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Forming of high aspect ratio conductive structure using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3791563