Forming an encapsulating layer after deposition of a...

Details Forming an encapsulating layer after deposition of a... Forming an encapsulating layer after deposition of a...

2000-02-23

2002-10-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C257S632000

Reexamination Certificate

active

06472336

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to formation of interconnect during fabrication of integrated circuits, and more particularly, to formation of an encapsulating layer after deposition of a dielectric comprised of corrosive material to prevent the corrosive material from degrading structures on subsequently processed semiconductor wafers.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the enhancement of the speed performance of integrated circuits. A common component of an integrated circuit is interconnect for coupling the various components of the integrated circuit. Referring to
FIG. 1
, a first interconnect structure
102
and a second interconnect structure
104
are formed on an insulating layer
106
of an integrated circuit fabricated on a semiconductor wafer
108
. For example, when the semiconductor wafer
108
is comprised of silicon, the insulating layer
106
is typically comprised of silicon dioxide, and the first and second interconnect structures
102
and
104
may be aluminum metal lines.
An insulating material
110
is deposited to surround the first and second interconnect structures
102
and
104
and to fill the gaps between the interconnect structures
102
and
104
. For enhancing the speed performance of the integrated circuit, the insulating material
110
surrounding the interconnect structures
102
and
104
is a dielectric material designed to have a low dielectric constant. A dielectric material with a low dielectric constant results in lower capacitance between the interconnect structures
102
and
104
. Such lower capacitance results in higher speed performance of the integrated circuit and also in lower power dissipation. In addition, such lower capacitance results in lower cross-talk between the interconnect structures
102
and
104
. Lower cross-talk between interconnect structures
102
and
104
is especially advantageous when the interconnect structures
102
and
104
are disposed closer together as device density continually increases.
A desired dielectric material having low dielectric constant for the insulating material
110
surrounding the interconnect structures
102
and
104
is fluorinated silicon dioxide, as known to one of ordinary skill in the art of integrated circuit fabrication. However, fluorine is corrosive for many integrated circuit structures on an semiconductor wafer. For example, fluorine is corrosive to interconnect structures comprised of aluminum and is corrosive to some types of insulating materials, as known to one of ordinary skill in the art of integrated circuit fabrication. A liner layer
112
is deposited conformally on the exposed surfaces of the interconnect structures
102
and
104
before fluorinated silicon dioxide is deposited to surround and protect the interconnect structures
102
and
104
from the corrosive fluorine.
Referring to
FIG. 2
, the interconnect structures
102
and
104
are initially patterned on the insulating layer
106
. Referring to
FIG. 3
, the liner layer
112
is deposited conformally on the exposed surfaces of the interconnect structures
102
and
104
. Referring to
FIG. 4
, fluorinated silicon dioxide is deposited to surround the interconnect structures
102
and
104
after the conformal deposition of the liner layer
112
. (Elements having the same reference number in FIGS.
1
,
2
,
3
, and
4
refer to elements having similar structure and function.)
The liner layer
112
is comprised of a dielectric material that is not corrosive to the interconnect structures
102
and
104
. For example, the liner layer
112
may be comprised of silicon dioxide for example. The liner layer
112
prevents the corrosive material such as fluorine of the fluorinated silicon dioxide from making contact with the interconnect structures
102
and
104
to prevent degradation of the interconnect structures
102
and
104
.
Processes for deposition of the liner layer
112
and fluorinated silicon dioxide
114
are performed in a deposition reaction chamber as known to one of ordinary skill in the art of integrated circuit fabrication. During deposition of the fluorinated silicon dioxide in such a deposition reaction chamber, fluorinated silicon dioxide is also deposited on the deposition reaction chamber. When a subsequent semiconductor wafer having exposed structures that are reactive with fluorine, such as bare interconnect structures thereon (as illustrated in
FIG. 2
) for example, is then placed in the deposition reaction chamber, the fluorine present in the deposition reaction chamber may degrade such structures of the subsequent semiconductor wafer.
Thus, a mechanism is desired for protecting any exposed structures of the subsequent semiconductor wafer placed into such a deposition reaction chamber when such exposed structures are reactive with fluorine.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a protective encapsulating layer is deposited on the prior semiconductor wafer having the corrosive fluorinated silicon dioxide and on the deposition reaction chamber to prevent contact of the corrosive fluorine with any exposed structures of the subsequent semiconductor wafer placed into the deposition reaction chamber when such exposed structures are corrosively reactive with the fluorine.
In one embodiment of the present invention, insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. A dielectric material is deposited to surround the interconnect structures and to fill any gaps between the interconnect structures. The dielectric material surrounding the interconnect structures is comprised of a corrosive material that degrades integrated circuit structures. Deposition of the corrosive dielectric material surrounding the interconnect structures is performed within the reaction chamber, and the corrosive dielectric material is deposited on the reaction chamber during deposition on the first semiconductor wafer. An encapsulating layer is formed over the corrosive dielectric material on the first semiconductor wafer and on the reaction chamber to prevent contact of the corrosive material to any exposed structures of a second semiconductor wafer to be subsequently placed into the reaction chamber when such exposed structures are reactive with the corrosive dielectric material.
The present invention may be used to particular advantage when the corrosive dielectric material is comprised of fluorinated silicon dioxide and when the encapsulating layer is comprised of unfluorinated silicon dioxide. When the interconnect structures are comprised of aluminum, a liner layer of unfluorinated silicon dioxide may be conformally deposited on such interconnect structures before deposition of the corrosive dielectric material.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.


REFERENCES:
patent: 5876798 (1999-03-01), Vassiliev
patent: 5937323 (1999-08-01), Orczyk et al.
patent: 6150010 (2000-11-01), Eissa
patent: 6153512 (2000-11-01), Chang et al.
patent: 6166427 (2000-12-01), Huang et al.
patent: 6274933 (2001-08-01), Abdelgadir et al.

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