Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-16
2004-01-27
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C257S295000, C257S310000
Reexamination Certificate
active
06682973
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of an interfacial layer in devices with a high-K dielectric material layer on a silicon substrate.
BACKGROUND ART
Fabrication of a semiconductor device and an integrated circuit including the same begins with a semiconductor substrate and employs film formation, ion implantation, photolithographic, etching and deposition techniques to form various structural features in or on the semiconductor substrate to attain individual circuit components which are then interconnected to form ultimately an integrated circuit. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) circuits requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for large-scale and ultra large-scale integrated circuits employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is typically a thin gate dielectric material, which is usually referred to as a gate oxide since it is conventionally formed of silicon dioxide, and a conductive gate comprising conductive polysilicon or another conductive material. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices employing both p-type and n-type devices are formed on a common substrate. MOS technology offers advantages of significantly reduced power density and dissipation as well as reliability, circuit performance and cost advantages.
The drive towards increased miniaturization and the resultant limits of conventional gate oxide layers have served as an impetus for the development of newer, high dielectric constant (“high-K”) materials as substitutes for conventional silicon dioxide-based gate oxide layers. Since the drain current in a MOS device is inversely proportional to the gate oxide thickness, the gate oxide is typically made as thin as possible commensurate with the material's breakdown field and reliability. A device in which high-K dielectric materials may be useful is the MIRRORBIT™ flash memory cell available from Advanced Micro Devices, Inc., Sunnyvale, Calif.
Decreasing the thickness of the gate oxide layer between the gate electrode and the source/drain extension regions together with the relatively high electric field across the gate oxide layer, can undesirably cause charge carriers to tunnel across the gate oxide layer. This renders the transistor “leaky”, degrading its performance. To alleviate this problem, high-k dielectric materials are being substituted for oxide as the gate dielectric. Herein, a high-K gate oxide may be referred to as a high-K gate dielectric material layer, in order to emphasize that the gate dielectric comprises a high-K dielectric material rather than silicon dioxide.
One problem which has been encountered in integrating high-K dielectric materials into MOS devices, and other semiconductor devices such as EEPROMs and other flash memory devices, is the undesirable interaction between many high-K dielectric materials and the silicon used in other semiconductor device structures, or the undesirable interaction between the reaction conditions used to form high-K dielectric materials and the silicon, polysilicon or polysilicon-germanium upon which the high-K layer is formed. Of particular concern is the interaction between the silicon typically used for the semiconductor wafer and the high-K material used for the high-K gate dielectric material. In addition, of concern is the interaction between the polysilicon or polysilicon-germanium which may be used in a flash memory device and the high-K material which is formed thereover. Such undesirable interactions could be observed, for example, in SONOS-type devices and in floating gate flash memory cells.
One of the undesirable interactions which may occur is the uncontrolled oxidation of the silicon, polysilicon or polysilicon-germanium material in contact with a high-K gate dielectric material layer by oxidizing species used in forming the high-k dielectric material layer, and by the oxygen in the metal oxides of which most high-K dielectric materials are formed. Such oxides may be formed in addition to native oxide on the silicon surface and may form more readily when a native oxide is present. These interactions, and the native oxide, either lead to an undesirably thick oxide interface at the silicon-high-K interface, or lead to degradation of the K value of the high-K dielectric material by formation of a composite dielectric material having a K value lower than desired. In both cases, the overall equivalent oxide thickness of the gate dielectric is reduced.
Hence, it would be highly advantageous to develop a process that would permit the use of optimum materials in the formation of a high-K gate dielectric material, without the problems which result from oxidation of silicon, polysilicon or polysilicon-germanium upon which the high-K dielectric material is deposited. Accordingly, there exists a need for a process of forming a high-K dielectric material over a silicon, polysilicon or polysilicon-germanium substrate, while avoiding or minimizing oxidation or interaction of high-K dielectric material with the silicon, polysilicon or polysilicon-germanium substrate.
DISCLOSURE OF INVENTION
In one embodiment, the present invention relates to a process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, including steps of growing on the silicon substrate an interfacial layer of a silicon-containing dielectric material; and depositing on the interfacial layer a layer comprising at least one high-K dielectric material, in which the interfacial layer is grown by laser excitation of the silicon substrate in the presence of oxygen, nitrous oxide, nitric oxide, ammonia or a mixture of two or more thereof.
In another embodiment, the present invention relates to a process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, including steps of growing on the silicon substrate an interfacial layer of a dielectric material comprising silicon dioxide, silicon nitride, silicon oxynitride or a mixture thereof; and depositing on the interfacial layer by ALCVD, RTCVD or MOCVD a layer comprising at least one high-K dielectric material, in which the interfacial layer is grown by laser excitation of the silicon substrate in the presence of oxygen, nitrous oxide, nitric oxide, ammonia or a mixture of two or more thereof.
In another embodiment, an interfacial barrier layer may be deposited on the high-K dielectric material layer, after the high-K dielectric material layer has been deposited on the interfacial layer.
Following deposition of the foregoing layers, a polysilicon or polysilicon-germanium gate electrode layer may be deposited thereon. The polysilicon or polysilicon-germanium gate electrode layer may be deposited either directly on the high-K dielectric material layer or on the interfacial barrier layer deposited on the high-K dielectric material layer.
Thus, the present invention provides a solution to the problem of forming a high-K dielectric material layer on a silicon substrate or of forming a polysilicon gate electrode on a high-K dielectric material layer without oxidation of the silicon, polysilicon or polysilicon-germanium.
REFERENCES:
patent: 6210999 (2001-04-01), Gardner et al.
patent: 6291866 (2001-09-01), Wallace et al.
patent: 6291867 (2001-09-01), Wallace et al.
patent: 6319759 (2001-11-01),
Paton Eric N.
Xiang Qi
Yu Bin
Advanced Micro Devices , Inc.
Everhart Caridad
Luu Chuong A
Renner , Otto, Boisselle & Sklar, LLP
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