Formation of out-diffused bitline by laser anneal

Details Formation of out-diffused bitline by laser anneal Formation of out-diffused bitline by laser anneal

1998-08-19

2001-03-27

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S262000, C438S561000

Reexamination Certificate

active

06207493

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods of fabricating a vertical semiconductor memory structure and, in particular to methods of fabricating a vertical gate semiconductor memory structure wherein the bitline of the structure is buried beneath the transfer gate. More specifically, the present invention provides methods of manufacturing such memory structures by utilizing a laser annealing step to out-diffuse dopant material which is present inside of the trench into the semiconductor substrate.
BACKGROUND OF THE INVENTION
As is known to those skilled in the art, a semiconductor memory device such as a dynamic random access memory (DRAM) cell comprises a plurality of memory cells which are used to store a large quantity of information. Each memory cell includes a capacitor for storing electric charge and a field effect transistor for opening and closing charge and discharge passages of the capacitor. The number of bits on DRAM chips has been increasing by approximately 4× every three years; this has been achieved by reducing the cell size. Unfortunately, the smaller cell size also results in less area to fabricate the capacitor.
In early DRAM generations, the storage electrode of each capacitor which constitutes each memory cell, together with each corresponding field effect transistor, was formed in the shape of a planar plate over the field effect transistor. Because of this planar plate shape, the storage electrode surface area was abruptly reduced as the cell size decreased. In this regard, conventional methods for fabricating memory cells have difficulties in increasing the surface area of storage electrodes because they involve the formation of a storage electrode having a planar plate shape.
In order to maintain increased electrode area while reducing the size of the memory cells, vertical gate (or trench) semiconductor memory structures have been employed. W. Hwang, et al. “High Density Vertical DRAM Cell”, IBM Technical Disclosure Bulletin, Vol. 29, No. 5, October 1986, pp. 2335-2339 discloses a typical prior art high density vertical DRAM cell wherein the transfer device is oriented in the vertical direction and is positioned over the trench storage capacitor. A shallow trench filled with polysilicon or polycide serves as the MOS transfer device gate. A representation of the high density vertical trench DRAM cell disclosed in W. Hwang, et al. is reproduced herein in FIG.
1
. Specifically,
FIG. 1
comprises a semiconductor wafer containing a p
+
substrate
10
and a p epitaxial layer
12
. The vertical DRAM cell also contains trenches
14
that contain an oxide
itride/oxide liner
16
and n
+
polysilicon
18
. Atop of each trench
14
is crystalline n
+
layer
20
and wordline
22
composed of n
+
polysilicon positioned between each trench. A p-type epitaxial layer
24
is located on either side of wordline
22
and is formed on top of p epitaxial layer
12
and n
+
polysilicon
18
. The structure further includes bitlines
26
located on either sides of wordline
22
and field oxide regions
28
.
In some instances, it is desirable to bury the bitline below the transfer gate, see for example, co-assigned U.S. application Ser. No. 08/787,418, filed Jan. 22, 1997. This bitline is often times formed in prior art processes by etching a trench within a thin film of As-doped oxide, blanket patterning a resist film in the bottom of the trench, etching the oxide film from the sidewalls of the trench where the transfer device will be, and annealing the substrate to drive the As dopant into the silicon wafer so as to form a buried bitline.
A major problem with this prior art approach is that the foregoing type of patterning produces conductive loops in the bitline effectively creating a common source. If a design will use uniquely addressed bitlines as also described in the above co-pending U.S. patent application Ser. No. 08/787,418, the loops need to be trimmed by a resist masking process.
One example of such a trim process is shown top-down in the sequence of FIGS.
2
(
a
)-(
d
). In FIG.
2
(
a
), the rows of pillars
2
are surrounded by deposition of arsenic containing glass
4
. A lithographic mask
6
is printed in the resist (see, FIG.
2
(
b
)) exposing only the ends of the loops to the isotropic etch of the dopant source resulting in the structure shown in FIG.
2
(
c
). The high temperature drive will then diffuse arsenic into the silicon pillar forming two discrete diffused bitlines
8
on each side of the pillar as is shown in FIG.
2
(
d
). Moreover, this prior art approach provides a poor control of channel doping with non-vertical pillars. In view of these drawbacks in prior art manufacturing of buried bitlines, there is a continued need to develop a new method of forming a buried bitline in a vertical semiconductor memory cell that does not have any conductive loops associated therewith. Such a method would eliminate the need of an extra processing step, in this case trimming via resist patterning, that is required by prior art processes to eliminate the conductive loops.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a vertical memory cell that contains a buried bitline.
Another object of the present invention is to provide a method of forming a buried bitline in a vertical memory cell that does not contain any conductive loops associated therewith.
A still further object of the present invention is to provide a method whereby a buried bitline can be formed in a semiconductor memory cell such that extra processing steps such as trimming are totally eliminated; therefore providing a simple, yet cost effective method of forming vertical memory cells which contain a buried bitline below the transfer gate.
These and other objects and advantages can be achieved in the present invention by utilizing a laser annealing step to out-diffuse the bitline material, e.g. dopant, so as to provide a bitline that is below the transfer gate. Specifically, in one embodiment of the present invention there is provided a method of forming a vertical memory cell wherein the bitline is buried below the transfer gate of said cell, said method comprising the steps of:
(a) forming at least one trench region in a semiconductor substrate;
(b) forming a conformal layer in said at least one trench region and on exposed surfaces of said semiconductor substrate, wherein said conformal layer is a dopant source material that comprises a dopant carrying material and a dopant element that is capable of being released, i.e. out-diffused, upon exposure to laser light;
(c) depositing a recessable material on the structure provided in step (b);
(d) recessing some, but not all, of said recessable, material and said conformal dopant source material leaving a masked region of said recessable material on a layer of said conformal dopant source material in said at least one trench region;
(e) stripping the masked region of said recessable material;
(f) laser annealing the structure provided in step (e) to cause out-diffusion of the dopant element from the remaining recessed dopant source material into said semiconductor substrate;
(g) stripping any remaining recessed source material from said at least one trench region; and
(h) etching said out-diffused dopant to provide a buried bitline in said semiconductor substrate.
In another embodiment of the present invention, the dopant source material in the trench can be converted to an oxide during the laser annealing step by irradiating the same in the presence of oxygen. This embodiment of the present invention is particularly useful when a plasma polymerized methylsilane is used as the dopant carrying material. Additionally, in some instances, it may be easier to strip the oxide rather than the dopant source material formed in the trench.
In yet another embodiment of the present invention, the buried bitline is formed by a method which comprises the following steps:
(a) forming at least one trench region in a semiconductor substrate;
(b) implan

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