Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-26
2002-04-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S220000
Reexamination Certificate
active
06376312
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to non-volatile memory devices, and more particularly to a non-volatile memory device comprised of an array of vertical field effect transistor structures as flash memory cells with each vertical field effect transistor fabricated by growing a semiconductor material within an opening formed through doped insulating materials for defining the drain and source extension junctions of the vertical field effect transistor and through a layer of dummy material deposited between the doped insulating materials for defining the channel region of the vertical field effect transistor.
BACKGROUND OF THE INVENTION
A non-volatile memory device is comprised of an array of flash memory cells with each flash memory cell storing 1-bit of digital information, as known to one of ordinary skill in the art of electronics. Referring to
FIG. 1
, a flash memory cell
100
of a prior art non-volatile memory device includes a tunnel gate dielectric
102
comprised of silicon dioxide (SiO
2
) for example as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel gate dielectric
102
is disposed on a semiconductor substrate
103
. In addition, a floating gate electrode
104
, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel gate dielectric
102
. A control gate dielectric
106
, comprised of silicon dioxide (SiO
2
) for example as known to one of ordinary skill in the art of integrated circuit fabrication, is disposed over the floating gate electrode
104
. A control gate electrode
108
, comprised of a conductive material such as polysilicon for example, is disposed over the control gate dielectric
106
.
A drain junction
110
that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area
112
of the semiconductor substrate
103
toward a left sidewall of the floating gate electrode
104
in
FIG. 1. A
source junction
114
that is doped with the junction dopant is formed within the active device area
112
of the semiconductor substrate
106
toward a right sidewall of the floating gate electrode
104
of FIG.
1
. The active device area
112
of the semiconductor substrate
103
is defined by shallow trench isolation structures
116
that electrically isolate the flash memory cell
100
from other integrated circuit devices within the semiconductor substrate
103
.
During the program or erase operations of the flash memory cell
100
of
FIG. 1
, charge carriers are injected into or injected out of the floating gate electrode
104
through the tunnel gate dielectric
102
. Such variation of the amount of charge carriers within the floating gate electrode
104
alters the threshold voltage of the flash memory cell
100
, as known to one of ordinary skill in the art of electronics. For example, when electrons are the charge carriers that are injected into the floating gate electrode
104
, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are injected out of the floating gate electrode
104
, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell
100
, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell
100
for example, a voltage of +9 Volts is applied on the control gate electrode
108
, a voltage of +5 Volts is applied on the drain junction
110
, and a voltage of 0 Volts (or a small bias of 0.25 Volts for example) is applied on the source junction
114
and on the semiconductor substrate
103
. Alternatively, during erasing of the flash memory cell
100
, referring to
FIG. 2
, a voltage of −9.5 Volts is applied on the control gate electrode
108
, a voltage of 0 Volts is applied on the drain junction
110
, and a voltage of +4.5 Volts is applied on the source junction
114
and on the semiconductor substrate
103
. Elements having the same reference number in
FIGS. 1 and 2
refer to elements having similar structure and function.
Referring to
FIG. 3
, an alternative flash memory cell
150
is comprised of a charge storing gate dielectric stack
120
between the control gate electrode
108
and the semiconductor substrate
103
. Elements having the same reference number in
FIGS. 1
,
2
, and
3
refer to elements having similar structure and function. The charge storing gate dielectric stack
120
is comprised of a tunnel gate dielectric
120
formed on the semiconductor substrate
103
, a charge storing dielectric
122
formed on the tunnel gate dielectric
120
, and a control gate dielectric
124
formed on the charge storing dielectric
122
.
In one example of the charge storing gate dielectric stack
120
, the tunnel gate dielectric
120
is comprise of silicon dioxide (SiO
2
) having a thickness of about 100 angstroms, the charge storing dielectric
122
is comprised of silicon nitride (Si
3
N
4
) having a thickness of about 85 angstroms, and the control gate dielectric
124
is comprised of silicon dioxide (SiO
2
) having a thickness of about 100 angstroms, formed in an ONO (oxide-nitride-oxide) deposition process as known to one of ordinary skill in the art of integrated circuit fabrication. During the program or erase operations of the flash memory cell
150
of
FIG. 3
, charge carriers are injected into or injected out of the charge storing dielectric
122
through the tunnel gate dielectric
120
. Such variation of the amount of charge carriers within the charge storing dielectric
122
alters the threshold voltage of the flash memory cell
150
, as known to one of ordinary skill in the art of electronics.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
In the flash memory cell
100
or
150
of
FIGS. 1
,
2
, and
3
, as the dimensions including the length of the channel region between the drain
110
and the source
114
of the flash memory cell
100
or
150
are further scaled down to tens of nanometers, short-channel effects degrade the performance of the flash memory cell
100
or
150
. Short-channel effects that result due to the short length of the channel region between the drain junction
104
and the source junction
106
of the flash memory cell
100
or
150
are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the flash memory cell
100
or
150
become difficult to control with short-channel effects which may severely degrade the performance of the flash memory cell
100
or
150
.
In the conventional planar flash memory cell
100
or
150
of
FIGS. 1
,
2
and
3
, the gate stack (comprised of the tunnel gate dielectric
102
, the floating gate electrode
104
, the control gate dielectric
106
, and the control gate electrode
108
for the flash memory cell
100
, or comprised of the charge storing gate dielectric stack
120
,
122
, and
124
and the control gate electrode
108
for the flash memory cell
150
) is disposed over one plane of the channel region between the drain and source junctions
110
and
114
. However, as the dimensions of the flash memory cell
100
or
150
are further scaled down to tens of nanometers, control of charge accumulation within the channel region of the flash memory cell
100
or
150
from a plurality of planes of the channel region is desired to minimize short channel effects.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to fabrication of an array of flash memory cells for a non-volatile memory device with each flash memory cell of the array being com
Choi Monica H.
Hoang Quoc
Nelms David
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