Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-02-07
2006-02-07
Flynn, Nathan J. (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000, C438S206000
Reexamination Certificate
active
06995057
ABSTRACT:
A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. A single crystalline vertical transistor is formed along alternating sides of the pillar within a row of pillars. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A plurality of buried bit lines are formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells. Further, a plurality of word lines are included. Each word line is disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench.
REFERENCES:
patent: 4864375 (1989-09-01), Teng et al.
patent: 4896293 (1990-01-01), McElroy
patent: 4920065 (1990-04-01), Chin et al.
patent: 4926224 (1990-05-01), Redwine
patent: 4954854 (1990-09-01), Dhong et al.
patent: 4958318 (1990-09-01), Harari
patent: 5006909 (1991-04-01), Kosa
patent: 5010386 (1991-04-01), Groover, III
patent: 5017504 (1991-05-01), Nishimura et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5057896 (1991-10-01), Gotou
patent: 5072269 (1991-12-01), Hieda
patent: 5122848 (1992-06-01), Lee et al.
patent: 5135879 (1992-08-01), Richardson
patent: 5156987 (1992-10-01), Sandhu et al.
patent: 5177576 (1993-01-01), Kimura et al.
patent: 5216266 (1993-06-01), Ozaki
patent: 5365477 (1994-11-01), Cooper, Jr. et al.
patent: 5379255 (1995-01-01), Shah
patent: 5392245 (1995-02-01), Manning
patent: 5414287 (1995-05-01), Hong
patent: 5427972 (1995-06-01), Shimizu et al.
patent: 5432739 (1995-07-01), Pein
patent: 5460988 (1995-10-01), Hong
patent: 5519236 (1996-05-01), Ozaki
patent: 5563083 (1996-10-01), Pein
patent: 5574299 (1996-11-01), Kim
patent: 5616934 (1997-04-01), Dennison et al.
patent: 5636170 (1997-06-01), Seyyedy
patent: 5640342 (1997-06-01), Gonzalez
patent: 5644540 (1997-07-01), Manning
patent: 5691230 (1997-11-01), Forbes
patent: 5869369 (1999-02-01), Hong
patent: 5874760 (1999-02-01), Burns, Jr. et al.
patent: 5885864 (1999-03-01), Ma
patent: 5888868 (1999-03-01), Yamazaki et al.
patent: 5891773 (1999-04-01), Saitoh
patent: 5907170 (1999-05-01), Forbes et al.
patent: 5909618 (1999-06-01), Forbes et al.
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5952039 (1999-09-01), Hong
patent: 5973352 (1999-10-01), Noble
patent: 5973356 (1999-10-01), Noble et al.
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6013548 (2000-01-01), Burns, Jr. et al.
patent: 6034389 (2000-03-01), Burns, Jr. et al.
patent: 6040218 (2000-03-01), Lam
patent: 6066869 (2000-05-01), Noble et al.
patent: 6072209 (2000-06-01), Noble et al.
patent: 6077745 (2000-06-01), Burns, Jr. et al.
patent: 6104061 (2000-08-01), Forbes et al.
patent: 6114725 (2000-09-01), Furukawa et al.
patent: 6124729 (2000-09-01), Noble et al.
patent: 6134175 (2000-10-01), Forbes et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6153468 (2000-11-01), Forbes et al.
patent: 6174784 (2001-01-01), Forbes
patent: 6184549 (2001-02-01), Furukawa et al.
patent: 6208164 (2001-03-01), Noble et al.
patent: 6211015 (2001-04-01), Noble
patent: 6219299 (2001-04-01), Forbes et al.
patent: 6222788 (2001-04-01), Forbes et al.
patent: 6238976 (2001-05-01), Noble et al.
patent: 6252267 (2001-06-01), Noble, Jr.
patent: 6377070 (2002-04-01), Forbes
patent: 6380765 (2002-04-01), Forbes et al.
patent: 6424001 (2002-07-01), Forbes et al.
patent: 6437389 (2002-08-01), Forbes et al.
patent: 6448601 (2002-09-01), Forbes et al.
patent: 6486027 (2002-11-01), Noble et al.
patent: 6496034 (2002-12-01), Forbes et al.
patent: 6531727 (2003-03-01), Ahn et al.
patent: 6559491 (2003-05-01), Forbes et al.
patent: 6566682 (2003-05-01), Forbes
patent: 6639268 (2003-10-01), Forbes et al.
patent: 6664806 (2003-12-01), Forbes et al.
patent: 6680508 (2004-01-01), Rudeck
patent: 6689660 (2004-02-01), Noble et al.
patent: 6720216 (2004-04-01), Forbes
patent: 2003/0008461 (2003-01-01), Forbes et al.
patent: 2003/0042512 (2003-03-01), Gonzalez
patent: 2003/0107402 (2003-06-01), Forbes et al.
patent: 2003/0218199 (2003-11-01), Forbes et al.
patent: 2004/0032773 (2004-02-01), Forbes et al.
patent: 2004/0042256 (2004-03-01), Forbes et al.
patent: 1358678 (2003-11-01), None
patent: 63-066963 (1988-03-01), None
patent: 2003-78075 (2003-10-01), None
patent: WO-03/063250 (2003-07-01), None
patent: WO-03/083947 (2003-10-01), None
Hergenrother, J. M., “The Vertical Replacement-Gate (VRG) MOSFET: A 50nm Vertical MOSFET with Lithography-Independent Gate Length”,IEEE, (1999),pp. 75-78.
Kalavade, P., et al., “A Novel-sub-10nm Transistor”,IEEE Device Research Conference, Denver, Co.,(2000),pp. 71-72.
Xuan, P., et al., “60nm Planarized Ultra-thin Body Solid Phase Epitaxy MOSFETs”,IEEE Device Research Conference, Denver, CO,(2000),pp. 67-68.
Pein, H., “A 3-D Sidewall Flash EPROM Cell and Memory Array”,IEEE Transactions on Electron Devices, 40,(Nov. 1993),2126-2127.
Pein, H., “Performance of the 3-D PENCIL Flash EPROM Cell and Memory Array”,IEEE Transactions on Electron Devices, 42,(Nov. 1995), 1982-1991.
Pein, H. B., “Performance of the 3-D Sidewall Flash EPROM Cell”,IEEE International Electron Devices Meeting, Technical Digest,(1993),11-14.
Stellwag, T.B., “Vertically-Integrated GaAs Bipolar DRAM Cell”,IEEE Transactions on Electron Devices, 38,(Dec. 1991),2704-2705.
Takato, H., “High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs”,IEEE International Electron Devices Meeting, Technical Digest,(1988),222-225.
Ahn Kie Y.
Forbes Leonard
Flynn Nathan J.
Micro)n Technology, Inc.
Quinto Kevin
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