Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With bumps on ends of lead fingers to connect to semiconductor
Reexamination Certificate
1999-12-16
2004-04-13
Pert, Evan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With bumps on ends of lead fingers to connect to semiconductor
C257S676000, C257S666000, C257S737000, C257S738000, C257S779000, C257S780000, C257S578000, C257S502000
Reexamination Certificate
active
06720642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improved package and method of packaging for a flip chip, and more particularly, to a flip chip wherein a die is attached to a leadframe that is then placed within a thinner package such that the back side of the die is exposed.
2. Description of the Prior Art
In power transistor packages, those in the art are generally still using chip and wire bond interconnect technology. It is difficult to simplify the manufacturing process flow as all process steps, such as, for example, die attach, wire bond, and molding are required. As a result, there is a limit placed on the maximum size for the die. Thus, power transistor packages are suited for single die applications since formation of an isolated metal pad for power transistor packages that include multiple dies is very difficult.
Recent attempts to improve packaging of chip devices have included directly coupling lead frames to the die. However, this technology does not lend itself well to the manufacture of thinner outline (or profile) packages. Hence, such packages, as well as those using wire bond interconnect technology, tend to be thick.
SUMMARY OF THE INVENTION
The present invention provides a chip device that includes a leadframe including a plurality of leads and a die coupled to the leadframe. The die includes a metallized back side as well as source and gate terminals opposite the metallized backside. The die is coupled to the leadframe such that the leads of the leadframe are directly coupled to the terminals. The chip device also includes a body including a window defined therein. The body is placed around at least a portion of the leadframe and the die such that the metallized back side of the die is adjacent the window.
In accordance with one aspect of the present invention, the die is coupled to the leadframe with solder bumps.
In accordance with another aspect of the present invention, the chip device includes two dies.
In accordance with a further aspect of the present invention, a method of making a chip device includes providing a leadframe including a plurality of leads and a die attach pad and post, coupling a die to the die attach pad and post and, encapsulating at least a portion of the leadframe and die such that a metallized back side of the die is adjacent a window defined within the package mold.
In accordance with another aspect of the present invention, the method includes configuring leads of the leadframe.
In accordance with another aspect of the present invention, the configuring of the leads includes removing mold flashes and resins from the leads, removing dambars, and solder plating the leads.
In accordance with a further aspect of the present invention, the leadframe is provided with preplated leads.
In accordance with yet another aspect of the present invention, the leadframe is provided with preplated leads and preformed leads.
In accordance with a further aspect of the present invention, the leadframe is provided with two die attach pads and posts, wherein a first die is coupled to a first die attach pad and post, and a second die is coupled to a second die attach pad and post.
In accordance with another aspect of the present invention, the die is coupled to the leadframe die attach pad and post via solder bumps, wherein the solder bumps are re-flowed.
Thus, the present invention provides a chip device that includes a thinner package, yet can accommodate a larger die. Indeed, up to a 70% increase in die area over wire bonded parts may be realized. Additionally, the present invention lends itself to packaging multiple dies in the same package. The present invention allows a die-to-die connection to be achieved using a low resistance path (leadframe based) capable of carrying high current. Furthermore, the present invention provides a simplified manufacturing process, especially in the embodiments where preplated and preformed leadframes are provided.
Other features and advantages of the present invention will be understood upon reading and understanding the detailed description of the preferred exemplary embodiments, found hereinbelow, in conjunction with reference to the drawings, in which like numerals represent like elements.
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Joshi Rajeev
Manatad Romel N.
Tangpuz Consuelo N.
Fairchild Semiconductor Corporation
Pert Evan
Thai Luan
Townsend and Townsend / and Crew LLP
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