Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-04-19
2005-04-19
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S266000
Reexamination Certificate
active
06881627
ABSTRACT:
Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a second contact layer vertically separated by an oxide layer. A single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical body region which separates an ultra thin single crystalline vertical first source/drain region and an ultra thin single crystalline vertical second source/drain region. A floating gate opposes the ultra thin single crystalline vertical body region, and a control gate separated from the floating gate by an insulator layer.
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Ahn Kie Y.
Forbes Leonard
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