Flash memory test system and method capable of test time...

Details Flash memory test system and method capable of test time... Flash memory test system and method capable of test time...

2007-08-07

2007-08-07

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S738000, C365S201000

Reexamination Certificate

active

10954834

ABSTRACT:
A flash memory test system capable of test time reduction and an electrical test method using the same: The invention provides a parallel tester that includes a first memory and a second memory. The first and second memories are used to each supply different data to identical addresses within a plurality of DUTs, thereby making it possible to conduct in parallel tests such as trim tests, repair tests, and invalid block masking test. Thus parallel testing is done to replace testing that was previously done serially.

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patent: 2003-0031789 (2003-04-01), None
English abstract of Korean Publication No. 2003-0031789.

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